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参数资料
| 型号： | LMP90079MH/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封装： | LEAD FREE, PLASTIC, MO-153, TSSOP-28 |
| 文件页数： | 15/62页 |
| 文件大小： | 1721K |
| 代理商： | LMP90079MH/NOPB |
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16.1.3 Selectable Gains (FGA & PGA)
LMP900xx provides two types of gain amplifiers: a fixed gain
amplifier (FGA) and a programmable gain amplifier (PGA).
FGA has a fixed gain of 16x or it can be bypassed, while the
PGA has programmable gain settings of 1x, 2x, 4x, or 8x.
Total gain is defined as FGA x PGA. Thus, LMP900xx pro-
vides gain settings of 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x
with true continuous background calibration.
The gain is channel specific, which means that one channel
can have one gain, while another channel can have the same
or a different gain.
The gain can be selected by programming the CHx_CONFIG:
GAIN_SEL bits.
16.1.4 Buffer (BUFF)
There is an internal unity gain buffer that can be included or
excluded from the signal path. Including the buffer provides a
high input impedance but increases the power consumption.
When gain
≥ 16, the buffer is automatically included in the
signal path. When gain < 16, including or excluding the buffer
from the signal path can be done by programming the
CHX_CONFIG: BUF_EN bit.
16.1.5 Internal/External CLK Selection
LMP900xx allows two clock options: internal CLK or external
CLK (crystal (XTAL) or clock source).
There is an “External Clock Detection” mode, which detects
the external XTAL if it is connected to XOUT and XIN. When
operating in this mode, the LMP900xx shuts off the internal
clock to reduce power consumption. Below is a flow chart to
help set the appropriate clock registers.
30169778
FIGURE 4. CLK Register Settings
The recommended value for the external CLK is discussed in
the next sections.
16.1.6 Programmable ODRs
If using the internal CLK or external CLK of 3.5717 MHz, then
the output date rates (ODR) can be selected (using the
ODR_SEL bit) as:
1. 13.42/8 = 1.6775 SPS
2. 13.42/4 = 3.355 SPS
3. 13.42/2 = 6.71SPS
4. 13.42 SPS
5. 214.65/8 = 26.83125 SPS
6. 214.65/4 = 53.6625 SPS
7. 214.65/2 = 107.325 SPS
8. 214.65 SPS (default)
If the internal CLK is not being used and the external CLK is
not 3.5717 MHz, then the ODR will be different. If this is the
case, use the equation below to calculate the new ODR val-
ues.
ODR_Base1 = (CLK
EXT) / (266,240)
ODR_Base2 = (CLK
EXT) / (16,640)
ODR1 = (ODR_Base1) / n, where n = 1,2,4,8
ODR2 = (ODR_Base2) / n, where n = 1,2,4,8
For example, a 3.6864 MHz XTAL or external clock has the
following ODR values:
ODR_Base1 = (3.6864 MHz) / (266,240) = 13.85 SPS
ODR_Base2 = (3.6864 MHz) / (16,640) = 221.54 SPS
ODR1 = (13.85 SPS) / n = 13.85, 6.92, 3.46, 1.73 SPS
ODR2 = (221.54 SPS) / n = 221.54, 110.77, 55.38, 27.69 SPS
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LMP90079MHX/NOPB | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| LMP90080 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Sensor AFE System: Multi-Channel, Low-Power 16-Bit |
| LMP90080MH/NOPB | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| LMP90080MHE/NOPB | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| LMP90080MHX/NOPB | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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