参数资料
型号: LMR10510YSDDEMO/NOPB
厂商: National Semiconductor
文件页数: 15/26页
文件大小: 0K
描述: BOARD EVAL FOR LMR10510
标准包装: 1
系列: SIMPLE SWITCHER®
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 1.8V
电流 - 输出: 1A
输入电压: 3 V ~ 5.5 V
稳压器拓扑结构: 降压
频率 - 开关: 3MHz
板类型: 完全填充
已供物品:
已用 IC / 零件: LMR10510
SNVS727B – OCTOBER 2011 – REVISED APRIL 2013
The first step is to determine R θ JA of the application. The LMR10510 has over-temperature protection circuitry.
When the silicon temperature reaches 165°C, the device stops switching. The protection circuitry has a
hysteresis of about 15°C. Once the silicon temperature has decreased to approximately 150°C, the device will
start to switch again. Knowing this, the R θ JA for any application can be characterized during the early stages of
the design one may calculate the R θ JA by placing the PCB circuit into a thermal chamber. Raise the ambient
temperature in the given working application until the circuit enters thermal shutdown. If the SW-pin is monitored,
it will be obvious when the internal PFET stops switching, indicating a junction temperature of 165°C. Knowing
the internal power dissipation from the above methods, the junction temperature, and the ambient temperature
R θ JA can be determined.
R T JA =
165° - Ta
P INTERNAL
Once this is determined, the maximum ambient temperature allowed for a desired junction temperature can be
found.
An example of calculating R θ JA for an application using the LMR10510 is shown below.
A sample PCB is placed in an oven with no forced airflow. The ambient temperature was raised to 147°C, and at
that temperature, the device went into thermal shutdown.
From the previous example:
P INTERNAL = 149 mW
R T JA =
165°C - 147°C
149 mW
= 121°C/W
Since the junction temperature must be kept below 125°C, then the maximum ambient temperature can be
calculated as:
T j - (R θ JA x P LOSS ) = T A
125°C - (121°C/W x 149 mW) = 107°C
WSON Package
Figure 24. Internal WSON Connection
For certain high power applications, the PCB land may be modified to a "dog bone" shape (see Figure 25 ). By
increasing the size of ground plane, and adding thermal vias, the R θ JA for the application can be reduced.
Copyright ? 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMR10510
15
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