参数资料
型号: LMX1501AM
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: XO, clock
英文描述: PLLatinumTM 1.1 GHz Frequency Synthesizer for RF Personal Communications
中文描述: PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO16
封装: 0.150 INCH, PLASTIC, SOP-16
文件页数: 10/22页
文件大小: 367K
代理商: LMX1501AM
Functional Description
The simplified block diagram below shows the 19-bit data register, the 14-bit R Counter and the S Latch, and the 18-bit
N Counter (intermediate latches are not shown). The data stream is clocked (on the rising edge) into the DATA input, MSB first.
If the Control Bit (last bit input) is HIGH, the DATA is transferred into the R Counter (programmable reference divider) and the
S Latch (prescaler select: 64/65 or 128/129). If the Control Bit (LSB) is LOW, the DATA is transferred into the N Counter
(programmable divider).
TL/W/12340–19
PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) AND PRESCALER SELECT (S LATCH)
If the Control Bit (last bit shifted into the Data Register) is HIGH, data is transferred from the 19-bit shift register into a 14-bit
latch (which sets the 14-bit R Counter) and the 1-bit S Latch (S15, which sets the prescaler: 64/65 or 128/129). Serial data
format is shown below.
TL/W/12340–20
14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO
(R COUNTER)
Divide
Ratio
R
14
S
13
S
12
S
11
S
10
S
S
9
S
8
S
7
S
6
S
5
S
4
S
3
S
2
S
1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
#
0
#
0
#
0
#
0
#
0
#
0
#
0
#
0
#
0
#
0
#
0
#
1
#
0
#
0
#
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes:
Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 16383
S1 to S14: These bits select the divide ratio of the programmable
reference divider.
C: Control bit (set to HIGH level to load R counter and S Latch)
Data is shifted in MSB first.
1-BIT PRESCALER SELECT
(S LATCH)
Prescaler
Select
P
15
S
128/129
0
64/65
1
10
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