- 您现在的位置：买卖IC网 > PDF目录67756 > LMX1602MDA (NATIONAL SEMICONDUCTOR CORP) PLL FREQUENCY SYNTHESIZER, 1100 MHz, UUC PDF资料下载
参数资料
| 型号： | LMX1602MDA |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 1100 MHz, UUC |
| 封装： | DIE |
| 文件页数： | 2/19页 |
| 文件大小： | 238K |
| 代理商： | LMX1602MDA |
2.0
Programming Description (Continued)
1.1 GHz option (12 bit)
MAIN_B_CNTR
Divide Ratio
11
10
9876543210
3
000000000011
4
000000000100
4,095
111111111111
Note 14: Divide ratio: 3 to 4,095 (Divide ratios less than 3 are prohibited)
MAIN_B_CNTR
≥ MAIN_A_CNTR.
See section 2.3.7 for calculation of VCO output frequency.
2.3.7
Pulse Swallow Function
The N divider counts such that it divides the VCO RF frequency by (P+1) for A times, and then divides by P for (B – A ) times.
The B value (B_CNTR) must be
≥ 3. The continuous divider range for the Main PLL N divider is from 992 to 65,535 for 2 GHz
option, from 240 to 65,535 for 1.1 GHz option, and from 56 to 32,767 for 500 MHz option. Divider ratios less than the minimum
value are achievable as long as the binary counter value is greater than or equal to the swallow counter value (B_CNTR
≥
A_CNTR).
f
VCO =Nx(fOSC /R)
N=(P x B) + A
f
VCO:
Output frequency of external voltage controlled oscillator (VCO)
f
OSC:
Output frequency of the external reference frequency oscillator (input to OSC
IN).
R:
Preset divide ratio of binary programmable reference counter (R_CNTR)
N:
Preset divide ratio of main programmable integer N counter (N_CNTR)
B:
Preset divide ratio of binary programmable B counter (B_CNTR)
A:
Preset value of binary 4-bit swallow A counter (A _CNTR)
P:
Preset modulus of dual modulus prescaler (P = 32 for 2 GHz option, P=16 for 1.1 GHz option, and P=8 for 500 MHz
option)
2.4
CHARGE PUMP CONTROL WORD (CP_WORD)
MSB
LSB
AUX_CP_GAIN
MAIN_CP_GAIN
AUX_PD_POL
MAIN_PD_POL
BIT
LOCATION
FUNCTION
0
1
AUX_CP_GAIN
MAIN_R[17]
Aux Charge Pump Current Gain
LOW
HIGH
MAIN_CP_GAIN
MAIN_R[16]
Main Charge Pump Current Gain
LOW
HIGH
AUX_PD_POL
MAIN_R[15]
Aux Phase Detector Polarity
Negative
Positive
MAIN_PD_POL
MAIN_R[14]
Main Phase Detector Polarity
Negative
Positive
AUX_CP_GAIN (MAIN_R[17]) and MAIN_CP_GAIN (MAIN_R[16]) are used to select charge pump current magnitude either low
gain mode (160 A typ) or high gain mode (1600 A typ)
AUX_ PD_POL (MAIN_R[15]) and MAIN_ PD_POL (MAIN_R[14]) are respectively set to one when Aux or Main VCO character-
istics are positive as in (1) below. When VCO frequency decreases with increasing control voltage (2) PD_POL should set to zero.
LMX1600/LMX1601/LMX1602
www.national.com
10
相关PDF资料 |
PDF描述 |
|---|---|
| LMX2305WG-MLSX | PLL FREQUENCY SYNTHESIZER, 500 MHz, CDSO20 |
| LMX2305WG-MPR | PLL FREQUENCY SYNTHESIZER, 550 MHz, CDSO20 |
| 5962-9855003QXA | PLL FREQUENCY SYNTHESIZER, 550 MHz, CDSO20 |
| LMX2331TMX | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO20 |
| LMX2331TM | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LMX1602SLB | 制造商:NSC 制造商全称:National Semiconductor 功能描述:PLLatinum⑩ Low Cost Dual Frequency Synthesizer |
| LMX1602SLBX | 功能描述:IC FREQ SYNTH DL 1.1GHZ 16-LAMIN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:PLLatinum™ 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| LMX1602TM | 制造商:NSC 制造商全称:National Semiconductor 功能描述:PLLatinum⑩ Low Cost Dual Frequency Synthesizer |
| LMX1602TM/NOPB | 功能描述:IC PLL DUAL 1.1GHZ 16TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:PLLatinum™ 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| LMX1602TMX/NOPB | 功能描述:IC FREQ SYNTH DL 1.1GHZ 16-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:PLLatinum™ 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
发布紧急采购，3分钟左右您将得到回复。