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参数资料
| 型号： | LMX2354SLDX |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, CQCC24 |
| 封装： | LAMINATE, CSP-24 |
| 文件页数： | 8/26页 |
| 文件大小： | 453K |
| 代理商： | LMX2354SLDX |
Programming Description (Continued)
5.1.2 CMOS (Programmable CMOS outputs)
(IF_N[17]–IF_N[20])
MSB
LSB
FastLock
TEST
OUT_1
OUT_0
Note: Test bit is reserved and should be set to zero for normal usage.
5.1.3 Programmable CMOS Output Truth Table
Bit
Location
Function
0
1
OUT_0
IF_N[17]
OUT0 CMOS Output Pin
Level Set
LOW
HIGH
OUT_1
IF_N[18]
OUT1 CMOS Output Pin
Level Set
LOW
HIGH
Test
IF_N[19]
Fractional Test Bit
Normal Operation
No Fractional
Compensation
Fastlock
IF_N[20]
Fastlock Mode Select
CMOS Output
Fastlock Mode
Test Bit IF_N[19] controls the fractional spur compensation and should be set to 0 for normal operation. If the test bit is set to 1,
then the fractional spurs become much worse, but the phase noise improves about 5 dB.
When the Fastlock bit is set to 1, OUT_0 and OUT_1 are don’t care bits. Fastlock mode utilizes the OUT0 and OUT1 output pins
to synchronously switch between active low and TRI-STATE. The OUT0 = LOW state occurs whenever the RF loop’s CP_8X is
selected HIGH while the Fastlock bit is set HIGH (see programming description 4.2.2). The OUT0 pin reverts to TRI-STATE when
the CP_8X bit is LOW. Similarly for the IF loop, the synchronous activation of OUT1 = LOW or TRI-STATE, is dependent on
whether the CP_GAIN_8 is high or low respectively (see programming description 4.1.4).
5.1.4 3-BIT IF SWALLOW COUNTER DIVIDE RATIO (IF A COUNTER)
(IF_N[2]IF_N[4])
Swallow Count
IF_NA_CNTR
(A)
2
1
0
00
10
01
71
11
Note: Swallow Counter Value: 0 to 7
IF_NB_CNTR
≥ IF_NA_CNTR
Minimum continuous count = 56 ( A=0, B=7)
5.1.5 12-BIT IF PROGRAMMABLE COUNTER DIVIDE RATIO (IF B COUNTER)
(IF_N[5]–IF_N[16])
IF_NB_CNTR
Divide
Ratio
11
10
987654321
0
3
00000000001
1
4
00000000010
0
4095
11111111111
1
Note: Divide ratio: 3 to 4095 (Divide ratios less than 3 are prohibited)
IF_NB_CNTR
≥ IF_NA_CNTR
N divider continuous integer divide ratio 56 to 32,767.
LMX2354
www.national.com
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相关代理商/技术参数 |
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|---|---|
| LMX2354SLEX | 制造商:Texas Instruments 功能描述: |
| LMX2354TM | 制造商:Texas Instruments 功能描述:PLL Frequency Synthesizer Dual 10MHz to 2500MHz 24-Pin TSSOP Rail 制造商:Texas Instruments 功能描述:2.5GHZ/550MHZ PLL 2354 TSSOP24 制造商:Texas Instruments 功能描述:IC, DUAL FREQ SYNTHESIZER 2.5GHZ 24-TSSOP, PLL Type:Frequency Synthesis, Frequen |
| LMX2354TM | 制造商:Texas Instruments 功能描述:2.5GHZ/550MHZ PLL 2354 TSSOP24 |
| LMX2354TM/NOPB | 功能描述:IC PLATINUM SYNTHESIZER 24TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:PLLatinum™ 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| LMX2354TMX/NOPB | 功能描述:IC FREQ SYNTH 2.5GHZ 24-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:PLLatinum™ 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
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