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参数资料
| 型号： | LMX2364SLE |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2600 MHz, QCC24 |
| 封装： | MICRO, CSP-24 |
| 文件页数： | 6/22页 |
| 文件大小： | 258K |
| 代理商： | LMX2364SLE |
Programming Description (Continued)
2.8.1 RF_TOC Fastlock Timeout Counter, RF Synthesizer
The RF_TOC word controls the operation of the RF Fastlock circuitry as well as the function of the FLoRF output pin. When
RF_TOC is set to a value between 0 and 2, the RF Fastlock circuitry is disabled and the FloRF pin operates as a general purpose
CMOS TRI-STATE I/O. When RF_TOC is set to a value between 3 and 16383, the RF Fastlock mode is enabled and FloRF is
utilized as the RF Fastlock output pin. The value programmed into RF_TOC represents the number of phase comparison cycles
that the RF synthesizer will spend in the Fastlock state.
RF_TOC[13:0]
Fastlock Mode
Fastlock Period
[CP Events]
FLo RF Pin Functionality
0
Disabled
N/A
High Impedance
1
Disabled
N/A
Logic “0” State
2
Manual
N/A
Logic “0” State. Force RF Change Pump to 16 mA
3
Disabled
3
Logic “1” State
4
Enabled
4
FastLock
…
Enabled
…
FastLock
16,383
Enabled
16383
FastLock
2.8.2 RF_CP_FL Fastlock Charge Pump Gain, RF Synthesizer
The RF_CP_FL word is used to control the charge pump gain for the RF synthesizer when Fastlock is enabled and engaged. Four
different CP gains are supported ranging from 1 to 16 mA. Note that when RF Fastlock mode is disengaged or disabled the CP
Gain is controlled by RF_CP[1:0].
RF_CP_FL[1:0]
CP Current
01 mA
14 mA
28 mA
316 mA
2.8.3 RF_OM RF Synthesizer Operating Mode
RF_OM controls the operating mode of the RF synthesizer. The various operating modes are described below:
RF Synthesizer Operating Mode Descriptions
RF_OM
FE<MISC[16]>
Operating Mode
Operating Mode Description
0
INT
RF synthesizer always operates as an Integer N PLL
1
FRAC
RF synthesizer always operates as a Fractional N PLL
2
0
INTFRAC
RF synthesizer operates as a Fractional N PLL while Fastlock circuit
enabled and engaged, and dynamically switches to operating as an
integer N PLL upon disengaging of the Fastlock circuit. The amount of
time that the Fastlock circuit is engaged is a function of the RF_TOC
control word.
Programming RF_OM to a value of 3 is not supported. INTFRAC mode should never be selected if Fastlock is not being used.
When using the INTFRAC mode, all programming needs to be done based on the RF synthesizer being a Fractional N PLL. The
device automatically handles the switching in of the appropriate integer R and N divider ratios to support integer N PLL operation.
Note that the Fractional Enable Bit, FE (MISC[16]) needs to be set appropriately. Enabling the fractional compensation in INT or
INTFRAC mode always degrades performance. It is generally recommended to enable it in fractional mode, although there may
be some rare exceptions that it may be set to 0.
2.8.4 RF_CSRC Cycle Slip Reduction Control, RF Synthesizer
RF_CSRC controls the operation of the Cycle Slip Reduction Circuit. This circuit should be used eliminate the occurrence of
phase detector cycle slips when operating in FRAC Mode (RF_OM = 1). In all other operating modes RF_CSRC should be
disabled by programming RF_CSRC = 0. See Section TBD for details on how to use this function.
RF_CSRC
CSR Enabled
Sample Rate Reduction Factor
0
Disabled
N/A
1
Enabled
2
Enabled
4
3
Enabled
8
LMX2364
www.national.com
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| LMX2364SLEX | 制造商:NSC 制造商全称:National Semiconductor 功能描述:2.6 GHz PLLatinum Fractional RF Frequency Synthesizer with 850 MHz Integer IF Frequency Synthesizer |
| LMX2364SLEX/NOPB | 功能描述:IC FREQ SYNTH 2.6GHZ 24LAMUCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:PLLatinum™ 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| LMX2364TM | 制造商:NSC 制造商全称:National Semiconductor 功能描述:2.6 GHz PLLatinum Fractional RF Frequency Synthesizer with 850 MHz Integer IF Frequency Synthesizer |
| LMX2364TM/NOPB | 功能描述:IC FREQ SYNTH 2.6GHZ 24TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:PLLatinum™ 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| LMX2364TMX | 制造商:NSC 制造商全称:National Semiconductor 功能描述:2.6 GHz PLLatinum Fractional RF Frequency Synthesizer with 850 MHz Integer IF Frequency Synthesizer |
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