参数资料
型号: LMX2515LQ0701/NOPB
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 26 MHz, QCC28
封装: 5 X 5 MM, 0.75 MM HEIGHT, LLP-28
文件页数: 17/17页
文件大小: 254K
代理商: LMX2515LQ0701/NOPB
Functional Description
GENERAL
The LMX2515 is a highly integrated frequency synthesizer
system for Japan PDC wireless communication systems.
The LMX2515LQ0701 supports operation for 800 MHz band
and the LMX2515LQ1321 supports operation for 1500 MHz
band.
The LMX2515 includes all functional blocks for the RF PLL
including RF VCO, frequency divider, PFD, and loop filter.
Only external passive elements for the RF VCO tank
(LMX2515LQ0701 only) and supply bypassing are required
to complete the RF synthesizer.
The LMX2515 uses a patent pending Fractional-N synthe-
sizer architecture based on a delta sigma modulator to sup-
port fine frequency resolution. Four of the most common
reference frequencies for PDC applications, 12.6 MHz, 14.4
MHz, 25.2 MHz and 26.0 MHz, are supported. The unique
feature of this architecture is its low spurious modulation
effect.
The use of a fractional synthesizer based on delta sigma
modulator allows for fast lock-up and system set-up times,
which reduces system power consumption. The loop filter is
included in the circuit to minimize the external noise coupling
and reduce the form factor applicable to the board level
application.
RF_PLL SECTION
Frequency Selection
The divide ratio can be calculated using the following equa-
tions:
f
VCO = {8 x RF_B + RF_A + (RF_FN / FD)} x (fOSC / R) where
(RF_A < RF_B) for LMX2515LQ1321
f
VCO = {4 x RF_B + RF_A + (RF_FN / FD)} x (fOSC / R) where
(RF_A < RF_B) for LMX2515LQ0701
f
VCO: Output frequency of voltage controlled oscillator (VCO)
RF_B: Preset divide ratio of binary 4-bit programmable
counter (2
≤ RF_B ≤ 15)
RF_A: Preset divide ratio of binary 3-bit swallow counter (0
RF_A
≤ 7 for LMX2515LQ1321 and 0 ≤ RF_A ≤ 3 for
LMX2515LQ0701)
RF_FN: Preset numerator of binary 10-bit modulus counter
(0
≤ RF_FN < FD)
FD: Preset denominator for modulus counter (FD = f
OSC/(R
Xf
CH) where fCH is the channel spacing)
f
OSC: Reference oscillation frequency
R: Internal reference oscillator frequency divider (1 for 12.6
MHz and 14.4 MHz, 2 for 25.2 MHz and 26.0 MHz)
The denominator, FD, in the above equation is dependent on
the channel spacing and reference oscillator frequency. The
channel spacing will change based on the Rx/Tx and RF-
_SEL bits. Table 6 in the R0 Register section summarizes
the values of FD.
VCO Frequency Tuning
The center frequency of the LMX2515 RF VCO is deter-
mined by the resonant frequency of the tank circuit, illus-
trated in Figure 1. With an internal fixed bonding-wire induc-
tor and an external inductor, the center frequency of the VCO
is given as follows:
20068810
where C
total is the total capacitance of the VCO, including
the parasitic capacitance and the nominal self-tuning capaci-
tance. Note, for the LMX2515LQ0701, the external induc-
tance consists of the PCB traces and lumped element induc-
tor. The output frequency tuning range can be optimized for
the specific application by selecting the appropriate external
inductance. Refer to LMX2515LQ0701 Tuning Range vs.
External Inductance plot to aid in selecting the appropriate
external inductance. Care should be taken to ensure proper
frequency coverage when choosing the tolerance of the
lumped element inductor.
For the LMX2515LQ1321, the internal bonding-wires provide
the necessary inductance to set the VCO center frequency
and no external inductance is required.
In real implementation, the inductance of L
fixed and Lexternal
can vary from its nominal value. The LMX2515 utilizes a
built-in tracking algorithm to compensate for variations up to
±15% and tunes the VCO to the required frequency. During
the frequency acquisition period, the loop bandwidth is ex-
tended to achieve the frequency lock. After the frequency
lock, the loop bandwidth of the PLL is set to the nominal
value and the phase lock is achieved. The transition be-
tween the two operating modes is very smooth and ex-
tremely fast to meet the stringent PDC requirements for lock
time and phase noise.
POWER DOWN MODE
The LMX2515 includes the power down mode to reduce the
power consumption. The LMX2515 enters the power down
mode either by taking the CE pin LOW or by setting the
RF_PD bit in the R0 register. If the CE pin is set LOW, the
circuit is powered down regardless of the register values.
When the CE pin is HIGH, the RF_PD bit controls power to
the RF circuitry. Data can be written to the registers even
when the CE pin is set LOW. The following truth table
summarizes the power down logic.
20068805
FIGURE 1. External Inductor Connection
LMX2515
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