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| 型号： | LMZ14201EXTTZX-ADJ |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING REGULATOR, PSSO7 |
| 封装： | 10.16 X 13.77 MM, 4.57 MM HEIGHT, ROHS COMPLIANT, TO-PMOD-7 |
| 文件页数： | 4/18页 |
| 文件大小： | 3944K |
| 代理商： | LMZ14201EXTTZX-ADJ |
V
IN = 12V, VO = 3.3V, IO = 1 A / 0.25 A
30117612
The approximate formula for determining the DCM/CCM
boundary is as follows:
I
DCBVO*(VIN–VO)/(2*10 μH*fSW(CCM)*VIN) (16)
Following is a typical waveform showing the boundary condi-
tion.
Transition Mode Operation
V
IN = 24V, VO = 3.3V, IO = 0.29 A
30117614
The inductor internal to the module is 10
μH. This value was
chosen as a good balance between low and high input voltage
applications. The main parameter affected by the inductor is
the amplitude of the inductor ripple current (I
LR). ILR can be
calculated with:
I
LR P-P=VO*(VIN- VO)/(10H*fSW*VIN) (17)
Where V
IN is the maximum input voltage and fSW is deter-
mined from equation 10.
If the output current I
O is determined by assuming that IO =
I
L, the higher and lower peak of ILR can be determined. Be
aware that the lower peak of I
LR must be positive if CCM op-
eration is required.
POWER DISSIPATION AND BOARD THERMAL
REQUIREMENTS
For the design case of V
IN = 24V, VO = 3.3V, IO = 1A, TAMB
(MAX) = 85°C , and TJUNCTION = 125°C, the device must see a
thermal resistance from case to ambient of less than:
θ
CA< (TJ-MAX — TAMB(MAX)) / PIC-LOSS - θJC (18)
Given the typical thermal resistance from junction to case to
be 1.9 °C/W. Use the 85°C power dissipation curves in the
Typical Performance Characteristics section to estimate the
P
IC-LOSS for the application being designed. In this application
it is 0.52W.
θ
CA = (125 — 85) / 0.52W — 1.9 = 75
To reach
θ
CA = 75, the PCB is required to dissipate heat ef-
fectively. With no airflow and no external heat, a good esti-
mate of the required board area covered by 1 oz. copper on
both the top and bottom metal layers is:
Board Area_cm2 = 500°C x cm2/W /
θ
JC (19)
As a result, approximately 6 square cm of 1 oz copper on top
and bottom layers is required for the PCB design. Additional
area will decrease die temperature proportionately. The PCB
copper heat sink must be connected to the exposed pad. Ap-
proximately thirty six, 10mils (254
μm) thermal vias spaced
59mils (1.5 mm) apart must connect the top copper to the
bottom copper. For an example of a high thermal performance
PCB layout of approximately 31 square cm area. Refer to the
Evaluation Board application note AN-2024. For more infor-
mation on thermal design see AN-2020 and AN-2026.
PC BOARD LAYOUT GUIDELINES
PC board layout is an important part of DC-DC converter de-
sign. Poor board layout can disrupt the performance of a DC-
DC converter and surrounding circuitry by contributing to EMI,
ground bounce and resistive voltage drop in the traces. These
can send erroneous signals to the DC-DC converter resulting
in poor regulation or instability. Good layout can be imple-
mented by following a few simple design rules.
30117611
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize
the high di/dt paths during PC board layout. The high current
loops that do not overlap have high di/dt content that will
cause observable high frequency noise on the output pin if
the input capacitor (Cin1) is placed at a distance away from
the LMZ14201EXT. Therefore place C
IN1 as close as possible
to the LMZ14201EXT VIN and GND exposed pad. This will
minimize the high di/dt area and reduce radiated EMI. Addi-
tionally, grounding for both the input and output capacitor
should consist of a localized top side plane that connects to
the GND exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and en-
able components should be routed to the GND pin of the
device. This prevents any switched or load currents from
flowing in the analog ground traces. If not properly handled,
poor grounding can result in degraded load regulation or er-
ratic output voltage ripple behavior. Provide the single point
ground connection from pin 4 to EP.
3. Minimize trace length to the FB pin.
Both feedback resistors, R
FBT and RFBB, and the feed forward
capacitor C
FF, should be located close to the FB pin. Since
the FB node is high impedance, maintain the copper area as
small as possible. The trace are from R
FBT, RFBB, and CFF
www.national.com
12
LMZ14201EXT
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LMZ14201H | 制造商:NSC 制造商全称:National Semiconductor 功能描述:1A SIMPLE SWITCHER? Power Module for High Output Voltage |
| LMZ14201H_1106 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:1A SIMPLE SWITCHER?? Power Module for High Output Voltage |
| LMZ14201H_13 | 制造商:TI 制造商全称:Texas Instruments 功能描述:LMZ14201H 1A SIMPLE SWITCHER?? Power Module for High Output Voltage |
| LMZ14201HEVAL/NOPB | 功能描述:电源管理IC开发工具 LMZ14201H EVAL BOARD RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
| LMZ14201HEVAL/NOPB | 制造商:Texas Instruments 功能描述:EVAL BOARD, LMZ14201H 12V, 1A REGULATOR |
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