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参数资料
| 型号： | LMZ1601-7RD9AHFU |
| 厂商： | POWER-ONE INC |
| 元件分类： | 电源模块 |
| 英文描述： | 1-OUTPUT AC-DC REG PWR SUPPLY MODULE |
| 封装： | 168.50 X 111.20 MM, 38.70 MM HEIGHT, METAL, CASE M02, MODULE |
| 文件页数： | 9/24页 |
| 文件大小： | 536K |
| 代理商： | LMZ1601-7RD9AHFU |
M-Family
DC-DC Converters <100 W
Rugged Environment
7 - 18
Edition 2/96 - Melcher AG
MELCHER
The Power Partners.
7.1
Option D Undervoltage monitor
The input and/or output undervoltage monitoring circuit op-
erates independently of the built-in input undervoltage lock-
out circuit. A logic "low" (JFET output) or "high" signal (NPN
output) is generated at pin 5 as soon as one of the moni-
tored voltages drops below the preselected threshold level
Ut. The return for this signal is Vo1– (pin 23). The D output
recovers when the monitored voltage(s) exceed(s)
Ut+Uh.
JFET output (D0…D4):
Connector pin D is internally connected via the drain-
source path of a JFET (self-conducting type) to the nega-
tive potential of output 1.
UD
≤ 0.4 V (logic low) corresponds
to a monitored voltage level (
Ui and/or Uo1) < Ut. The cur-
rent
ID through the JFET should not exceed 2.5 mA. The
JFET is protected by a 0.5 W Zener diode of 8.2 V against
external overvoltages.
Ui, Uo1 status
D output,
UD
Ui or Uo1 < Ut
low, L,
UD ≤ 0.4 V at ID = 2.5 mA
Ui and Uo1 > Ut + Uh
high, H,
I D
≤ 25 A at UD = 5.25 V
NPN output (D5...D9):
Connector pin D is internally connected via the collector-
emitter path of a NPN transistor to the negative potential of
output 1.
UD < 0.4 V (logic low) corresponds to a monitored
voltage level (
Ui and/or Uo1) > Ut + Uh. The current ID
through the open collector should not exceed 20 mA. The
NPN output is not protected against external overvoltages.
UD should not exceed 40 V.
Ui, Uo1 status
D output,
UD
Ui or Uo1 < Ut
high, H,
I D ≤ 25 A at UD = 40 V
Ui and Uo1 > Ut + Uh
low, L,
UD
≤ 0.4 V at ID = 20 mA
20
23
5
Vo1+
Vo1–
D
UD
ID
Vi+
Vi–
29
32
Rp
Table 19: Undervoltage monitor functions
Output type
Monitoring
Minimum adjustment range
Typical hysteresis
Uh [ % of Ut]
JFET
NPN
Ui
Uo1
of threshold level
Ut
for
Ut min...Ut max
Uti
Uto
Uhi
Uho
D1
D5
no
yes
–
3.5 V...48 V 1
–
2.3...1
D2
D6
yes
no
Ui min...Ui max 1–
3.0...0.5
–
D3
D7
yes
Ui min...Ui max 1
0.95...0.98
Uo1 2
3.0...0.5
"0"
D4
D8
no
yes
–
0.95...0.98
Uo1 2
–
"0"
D0
D9
no
yes
–
3.5 V...48 V 3
–
1.8...1
yes
no
Ui min...Ui max 3 4
–
2.2...0.4
–
yes
Ui min...Ui max 3 4
0.95...0.98
Uo1 2
2.2...0.4
"0"
1 Threshold level adjustable by potentiometer (not recommended for mobile applications)
2 Fixed value between 95% and 98% of Uo1 (tracking)
3 Fixed value, resistor-adjusted according to customer's specifications
±2% at 25°C; individual type number is determined by Melcher
4 Adjusted at Io nom
Fig. 17
Options D0...D4, JFET output
Fig. 18
Options D5...D9, NPN output
5
23
20
Vo1+
Vo1–
D
UD ≤ 6 V
ID
29
32
Vi+
Vi–
Rp
The threshold level
Ut is either adjustable by a potentio-
meter, accessible through a hole in the front cover, or is fac-
tory adjusted to a fixed value specified by the customer.
Option D exists in various versions D0...D9 as shown in the
following table.
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