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参数资料
| 型号： | LPC1225FBD64/301,1 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 11/61页 |
| 文件大小： | 0K |
| 描述： | MCU 32BIT 64K FLASH 8K 64-LQFP |
| 产品培训模块： | LPC1200 Series for Industrial Control |
| 特色产品： | LPC122x Cortex-M0 Microcontrollers |
| 标准包装： | 160 |
| 系列： | LPC1200 |
| 核心处理器： | ARM? Cortex?-M0 |
| 芯体尺寸： | 32-位 |
| 速度： | 45MHz |
| 连通性： | I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART |
| 外围设备： | 欠压检测/复位，DMA，POR，WDT |
| 输入/输出数： | 55 |
| 程序存储器容量： | 64KB（64K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 8x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 64-LQFP |
| 包装： | 托盘 |
| 其它名称： | 568-5159 LPC1225FBD64/301 |
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LPC122X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 August 2011
19 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
Supports memory-to-memory, memory-to-peripheral, and peripheral-to-memory
transfers.
Supports multiple DMA cycle types and multiple DMA transfer widths.
Performs all DMA transfers using the single AHB-Lite burst type.
7.8 CRC engine
The Cyclic Redundancy Check (CRC) engine with programmable polynomial settings
supports several CRC standards commonly used. To save system power and bus
bandwidth, the CRC engine supports DMA transfers.
7.8.1 Features
Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.
– CRC-CCITT: x16 + x12 + x5 + 1
– CRC-16: x16 + x15 + x2 + 1
– CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
Bit order reverse and 1’s complement programmable setting for input data and CRC
sum.
Programmable seed number setting.
Supports CPU programmed I/O or DMA back-to-back transfer.
Accept any size of data width per write: 8, 16 or 32-bit.
– 8-bit write: 1-cycle operation
– 16-bit write: 2-cycle operation (8-bit
2-cycle)
– 32-bit write: 4-cycle operation (8-bit
4-cycle)
7.9 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
7.9.1 Features
Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
Direction control of individual bits.
All I/O default to inputs after reset.
7.10 UARTs
The LPC122x contains two UARTs. UART0 supports full modem control and RS-485/9-bit
mode and allows both software address detection and automatic hardware address
detection using 9-bit mode.
The UARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LPC1225FBD64321 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash and 8 kB SRAM |
| LPC1225FBD64-321 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Up to 128 KB Flash and configurable peripherals for industrial control |
| LPC1226 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash and 8 kB SRAM |
| LPC1226FBD48 | 制造商:NXP 功能描述:M0 Core MCU |
| LPC1226FBD48/301 | 制造商:NXP Semiconductors 功能描述:MCU 96K FLASH CORTEX-M0 48LQFP 制造商:NXP Semiconductors 功能描述:MCU, 96K FLASH, CORTEX-M0, 48LQFP 制造商:NXP Semiconductors 功能描述:MCU, 96K FLASH, CORTEX-M0, 48LQFP; Controller Family/Series:LPC1200; Core Size:32bit; No. of I/O's:39; Supply Voltage Min:3V; Supply Voltage Max:3.6V; Digital IC Case Style:LQFP; No. of Pins:48; Program Memory Size:96KB; RAM Memory ;RoHS Compliant: Yes |
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