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参数资料
| 型号： | LPC2106FBD48/01,15 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 15/41页 |
| 文件大小： | 0K |
| 描述： | IC ARM7 MCU FLASH 128K 48-LQFP |
| 标准包装： | 250 |
| 系列： | LPC2100 |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 60MHz |
| 连通性： | I²C，Microwire，SPI，SSI，SSP，UART/USART |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 32 |
| 程序存储器容量： | 128KB（128K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 64K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.65 V ~ 3.6 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 48-LQFP |
| 包装： | 托盘 |
| 产品目录页面： | 704 (CN2011-ZH PDF) |
| 配用： | 568-4310-ND - EVAL BOARD LPC2158 W/LCD 568-4297-ND - BOARD EVAL LPC21XX MCB2100 622-1019-ND - BOARD FOR LPC2106 48-LQFP 622-1008-ND - BOARD FOR LPC9103 10-HVSON 622-1005-ND - USB IN-CIRCUIT PROG ARM7 LPC2K 568-1756-ND - BOARD EVAL FOR LPC210X ARM MCU |
| 其它名称： | 568-4367 935286617151 LPC2106FBD48/01-S |
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LPC2104_2105_2106_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 20 June 2008
22 of 41
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed
following a chip Reset and may be enabled by software. The program must congure and
activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The
PLL settling time is 100
s.
6.18.3 Reset and wake-up timer
Reset has two sources on the LPC2104/2105/2106: the RESET pin and Watchdog Reset.
The RESET pin is a Schmitt trigger input pin with an additional glitch lter. Assertion of
chip Reset by any source starts the wake-up timer (see wake-up timer description below),
causing the internal chip reset to remain asserted until the external Reset is de-asserted,
the oscillator is running, a xed number of clocks have passed, and the on-chip ash
controller has completed its initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is the Reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.
The wake-up timer ensures that the oscillator and other analog functions required for chip
operation are fully functional before the processor is allowed to execute instructions. This
is important at power on, all types of Reset, and whenever any of the aforementioned
functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the wake-up timer.
The wake-up timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufcient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of VDD ramp (in the case of power on), the type of crystal
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
6.18.4 Code security (Code Read Protection - CRP)
This feature of the LPC2104/2105/2106/01 allows the user to enable different levels of
security in the system so that access to the on-chip ash and use of the JTAG and ISP
can be restricted. When needed, CRP is invoked by programming a specic pattern into a
dedicated ash location. IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection:
1. CRP1 disables access to the chip via the JTAG and allows partial ash update
(excluding ash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and ash eld updates are needed but all sectors can
not be erased.
2. CRP2 disables access to the chip via the JTAG and only allows full ash erase and
update using a reduced set of the ISP commands.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LPC2106FHN48 | 制造商:NXP Semiconductors 功能描述:IC MCU ARM7 FLASH SMD HVQFN-48 制造商:NXP Semiconductors 功能描述:IC, MCU ARM7 FLASH, SMD, HVQFN-48 制造商:NXP Semiconductors 功能描述:MCU 16-Bit/32-Bit LPC2000 ARM7TDMI-S RISC 128KB Flash 1.8V/3.3V 48-Pin HVQFN EP Tray |
| LPC2106FHN48,551 | 功能描述:ARM微控制器 - MCU ARM7 128KF/64KR/I2C RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 处理器系列:STM32F373xx 数据总线宽度:32 bit 最大时钟频率:72 MHz 程序存储器大小:256 KB 数据 RAM 大小:32 KB 片上 ADC:Yes 工作电源电压:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 封装 / 箱体:LQFP-48 安装风格:SMD/SMT |
| LPC2106FHN48/00 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Single-chip 32-bit microcontrollers; 128 kB ISP/IAP flash with 16/32/64 kB RAM |
| LPC2106FHN48/01 | 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 60MHZ, HVQFN-48 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 60MHZ, HVQFN-48, Controller Family/Series:LPC2100, Core Size:1 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 60MHZ, HVQFN-48, Controller Family/Series:LPC2100, Core Size:16bit / 32bit, No. of I/O's:32, Supply Voltage Min:1.65V, Supply Voltage Max:1.95V, Digital IC Case Style:HVQFN, No. of Pins:48, Program Memory |
| LPC2106FHN48/01,55 | 功能描述:ARM微控制器 - MCU 128K FL/64K RAM/2 UART/I2C/SPI RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 处理器系列:STM32F373xx 数据总线宽度:32 bit 最大时钟频率:72 MHz 程序存储器大小:256 KB 数据 RAM 大小:32 KB 片上 ADC:Yes 工作电源电压:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 封装 / 箱体:LQFP-48 安装风格:SMD/SMT |
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