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参数资料
| 型号： | LPC3250FET296/01,5 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 12/57页 |
| 文件大小： | 0K |
| 描述： | IC ARM9 MCU 256K 296-TFBGA |
| 标准包装： | 126 |
| 系列： | LPC3200 |
| 核心处理器： | ARM9 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 266MHz |
| 连通性： | EBI/EMI，以太网，I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART，USB OTG |
| 外围设备： | DMA，I²S，LCD，电机控制 PWM，PWM，WDT |
| 输入/输出数： | 51 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 256K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 0.9 V ~ 3.6 V |
| 数据转换器： | A/D 3x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 296-TFBGA |
| 包装： | 托盘 |
| 其它名称： | 568-4962 935290766551 |
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LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
2 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
External memory controller for DDR and SDR SDRAM as well as for static devices.
Two NAND flash controllers: One for single-level NAND flash devices and the other for
multi-level NAND flash devices.
Master Interrupt Controller (MIC) and two Slave Interrupt Controllers (SIC), supporting
74 interrupt sources.
Eight channel General Purpose DMA (GPDMA) controller on the AHB that can be
used with the SD card port, the high-speed UARTs, I2S-bus interfaces, and SPI
interfaces, as well as memory-to-memory transfers.
Serial interfaces:
10/100 Ethernet MAC with dedicated DMA Controller.
USB interface supporting either device, host (OHCI compliant), or On-The-Go
(OTG) with an integral DMA controller and dedicated PLL to generate the required
48 MHz USB clock.
Four standard UARTs with fractional baud rate generation and 64 byte FIFOs. One
of the standard UARTs supports IrDA.
Three additional high-speed UARTs intended for on-board communications that
support baud rates up to 921 600 when using a 13 MHz main oscillator. All
high-speed UARTs provide 64 byte FIFOs.
Two SPI controllers.
Two SSP controllers.
Two I2C-bus interfaces with standard open-drain pins. The I2C-bus interfaces
support single master, slave, and multi-master I2C-bus configurations.
Two I2S-bus interfaces, each with separate input and output channels. Each
channel can be operated independently on three pins, or both input and output
channels can be used with only four pins and a shared clock.
Additional peripherals:
LCD controller supporting both STN and TFT panels, with dedicated DMA
controller. Programmable display resolution up to 1024
768.
Secure Digital (SD) memory card interface, which conforms to the SD Memory
Card Specification Version 1.01.
General Purpose (GP) input, output, and I/O pins. Includes 12 GP input pins, 24
GP output pins, and 51 GP I/O pins.
10-bit, 400 kHz Analog-to-Digital Converter (ADC) with input multiplexing from
three pins. Optionally, the ADC can operate as a touch screen controller.
Real-Time Clock (RTC) with separate power pin and dedicated 32 kHz oscillator.
NXP implemented the RTC in an independent on-chip power domain so it can
remain active while the rest of the chip is not powered. The RTC also includes a
32-byte scratch pad memory.
32-bit general purpose high-speed timer with a 16-bit pre-scaler. This timer
includes one external capture input pin and a capture connection to the RTC clock.
Interrupts may be generated using three match registers.
Six enhanced timer/counters which are architecturally identical except for the
peripheral base address. Two capture inputs and two match outputs are pinned out
to four timers. Timer 1 brings out a third match output, timers 2 and 3 bring out all
four match outputs, timer 4 has one match output, and timer 5 has no inputs or
outputs.
32-bit millisecond timer driven from the RTC clock. This timer can generate
interrupts using two match registers.
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