参数资料
| 型号： | LPC3250FET296,551 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 1/57页 |
| 文件大小： | 0K |
| 描述： | IC ARM9 MCU 256K 296-TFBGA |
| 特色产品： | LPC32x0 ARM926EJ-S Processor |
| 标准包装： | 126 |
| 系列： | LPC3200 |
| 核心处理器： | ARM9 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 266MHz |
| 连通性： | EBI/EMI，以太网，I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART，USB OTG |
| 外围设备： | DMA，I²S，LCD，电机控制 PWM，PWM，WDT |
| 输入/输出数： | 51 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 256K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 0.9 V ~ 3.6 V |
| 数据转换器： | A/D 3x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 296-TFBGA |
| 包装： | 托盘 |
| 配用： | 568-4743-ND - KIT LCD TOUCH 5.7" FOR LPC3250 568-4742-ND - MODULE DIMM LPC2478 ARM7 622-1030-ND - KIT LCD TOUCH 5.7" FOR LPC3250 |
| 其它名称： | 568-4533 935287084551 |
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1.
General description
The LPC3220/30/40/50 embedded microcontrollers were designed for low power, high
performance applications. NXP achieved their performance goals using a 90 nanometer
process to implement an ARM926EJ-S CPU core with a vector floating point co-processor
and a large set of standard peripherals including USB On-The-Go. The
LPC3220/30/40/50 operates at CPU frequencies of up to 266 MHz.
The NXP implementation uses a ARM926EJ-S CPU core with a Harvard architecture,
5-stage pipeline, and an integral Memory Management Unit (MMU). The MMU provides
the virtual memory capabilities needed to support the multi-programming demands of
modern operating systems. The ARM926EJ-S also has a hardware based set of DSP
instruction extensions, which includes single cycle MAC operations, and hardware based
native Jazelle Java Byte-code execution. The NXP implementation has a 32 kB
instruction cache and a 32 kB data cache.
For low power consumption, the LPC3220/30/40/50 takes advantage of NXP’s advanced
technology development to optimize intrinsic power and uses software controlled
architectural enhancements to optimize application based power management.
The LPC3220/30/40/50 also includes 256 kB of on-chip static RAM, a NAND flash
interface, an Ethernet MAC, an LCD controller that supports STN and TFT panels, and an
external bus interface that supports SDR and DDR SDRAM as well as static devices. In
addition, the LPC3220/30/40/50 includes a USB 2.0 full-speed interface, seven UARTs,
two I2C-bus interfaces, two SPI/SSP ports, two I2S-bus interfaces, two single output
PWMs, a motor control PWM, six general purpose timers with capture inputs and compare
outputs, a Secure Digital (SD) interface, and a 10-bit Analog-to-Digital Converter (ADC)
with a touch screen sense option.
2.
Features and benefits
ARM926EJ-S processor, running at CPU clock speeds up to 266 MHz.
Vector Floating Point (VFP) coprocessor.
32 kB instruction cache and 32 kB data cache.
Up to 256 kB of Internal SRAM (IRAM).
Selectable boot-up from various external devices: NAND flash, SPI memory, USB,
UART, or static memory.
Multi-layer AHB system that provides a separate bus for each AHB master, including
both an instruction and data bus for the CPU, two data busses for the DMA controller,
and another bus for the USB controller, one for the LCD, and a final one for the
Ethernet MAC. There are no arbitration delays in the system unless two masters
attempt to access the same slave at the same time.
LPC3220/30/40/50
16/32-bit ARM microcontrollers; hardware floating-point
coprocessor, USB On-The-Go, and EMC memory interface
Rev. 2 — 20 October 2011
Product data sheet
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