参数资料
型号: LPR2430ERADK
厂商: RFM
文件页数: 4/5页
文件大小: 0K
描述: RF DEV KIT FOR LPR2430
标准包装: 1
类型: 收发器,802.15.4
频率: 2.4GHz
适用于相关产品: LPR2430ERA
已供物品: 2 个板,天线,电池,线缆,CD,电源适配器
其它名称: 583-1171
LPR2430ERA I/O Pad Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Name
GND
ACTIVITY
LINK
GPIO0
(ADC_REF)
RADIO_TXD
RADIO_RXD
GPIO4
(/HOST_CTS )
GPIO5
(/HOST_RTS)
PWM0
GPIO2
(PWM1)
GPIO1
GPIO3
(RS485_EN)
PWM1
(GPIO2)
VCC
GND
GND
/RESET
ADC0
ADC1
RSVD
RSVD
RSVD
RSVD
ADC2
ADC_VDD
NC
NC
GND
NC
GND
I/O
-
O
O
I/O
O
I
I/O
I/O
O
I/O
I/O
I/O
O
I
-
-
I
I
I
-
-
-
-
I
O
-
-
-
-
-
Description
Power supply and signal ground. Connect to the host circuit board ground.
RF activity indicator. Output pulses high when a packet is sent or received.
Link indicator. Output is high when the radio has successfully joined a network.
Configurable digital I/O port 0. When configured as an output, the power-on state is also configurable. This pin can also
be configured as a reference voltage input for the ADCs, 0 to 3.3 V, 1.25 V typical.
Serial data output (UART) from the radio to the host.
Serial data input (UART) from the host to the radio.
Configurable digital I/O port 4. When configured as an output, the power-on state is also configurable. Also configurable
as UART flow control output. The LPR2430 sets this line low to indicate it is ready to accept data from the host on the
RADIO_RXD input. When the LPR2430 sets this line high, the host must stop sending data. The default state is GPIO4.
Configurable digital I/O port 5. When configured as an output, the power-on state is also configurable. Also configurable
as UART flow control input. The host sets this line low to allow data to flow from the RADIO_TXD pin. When the host sets
this line high, the LPR2430 will stop sending data to the host. The default state is GPIO5 .
Pulse-width modulated output 0 with internal low-pass filter. Provides a DAC function, 0 to 3.3 V.
Configurable digital I/O port 2. When configured as an output, the power-on state is also configurable. This pin is con-
nected to the input of the low-pass filter driving Pin 13, and is also configurable as a PWM output.
Configurable digital I/O port 1. When configured as an output, the power-on state is also configurable.
Configurable digital I/O port 3. When configured as an output, this high current port can sink up to 20 mA. The power-on
output state is also configurable. Can also be configured as active low transmit enable for controlling an RS485 or other
half-duplex bus driver.
GPIO2 (Pin 10) drives this pin through a low-pass filter. Provides a DAC function when GPIO2 is configured as a PWM
output.
Power supply input, +3.3 to +5.5 Vdc.
Power supply and signal grounds. Connect to the host circuit board ground.
Power supply and signal grounds. Connect to the host circuit board ground.
Active low module hardware reset. Hold this input low when the power supply input is less than 3.3 Vdc. The module firm-
ware boots up and will accept commands about 3 seconds after this input goes high.
11-bit ADC input 0. ADC full scale reading can be referenced to the module’s +3.3 V regulated supply, the ADC’s internal
+2.5 V reference, or ADC_REF (Pin 4).
ADC input 1. Same configuration options as ADC0.
Reserved pin. Leave unconnected.
Reserved pin. Leave unconnected.
Reserved pin. Leave unconnected.
Reserved pin. Leave unconnected.
ADC input 2. Same configuration options as ADC0.
Module’s +3.3 V regulated supply, used for ratiometric ADC readings. Current drain should be less than 5 mA.
No connection.
No connection.
RF ground. Connect to the host circuit board ground plane, and to shield when using coaxial cable.
No connection.
RF ground. Connect to the host circuit board ground plane, and to shield when using coaxial cable.
www.RFM.com E-mail: info@rfm.com
?2009 by RF Monolithics, Inc.
Page 4 of 5
LPR2430ERA - 06/19/09
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