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参数资料
| 型号： | LS7031 |
| 厂商： | LSI Corporation |
| 英文描述： | Connector Contact,SKT,CRIMP Terminal |
| 中文描述： | 6与8个十年闭锁及多计数器十年马鞍山 |
| 文件页数： | 1/4页 |
| 文件大小： | 47K |
| 代理商： | LS7031 |
6 DECADE MOS UP COUNTER WITH 8 DECADE LATCH AND MULTIPLEXER
FEATURES:
DC to 7.5 MHz Count Frequency
Multiplexed BCD Outputs
DC to 500kHz Scan Frequency
+4.75V to +15V Operation (V
DD
-V
SS
)
Compatible with CMOS Logic
High Input Noise Immunity
Ability to Latch External BCD Data in the two LSD Positions
Leading Zero Blanking with Decimal Point and Overflow Controls
All inputs protected
Low Power Dissipation
40 Pin DIP - See Figure 1
DESCRIPTION:
The LS7031 is a monolithic, ion implanted MOS, 6 decade up coun-
ter. The circuit includes latches, a multiplexer, leading zero blanking
and BCD data outputs.
CLOCK GENERATOR
The clock for the six decade counter (digit positions 3-8) is formed
from the internal ‘OR’ combination of B4/D2 and B8/D2 if LS7031
is used with external prescaling counters. When operated in this
fashion the maximum allowable propagaton delay between B4/D2
(H-L) and B8/D2 (L-H), measured at Vss - 1V, is 10ns. If used as
a straight six decade counter, clock pulses may be applied to in-
puts B4/D2 or B8/D2 with the unused input held low. In either mode
of operation total pulse width must be minimum 62ns. See Block
Diagram.
6 DECADE UP COUNTER
The six decade ripple through counter increments on the negative
edge of the input count pulse. Maximum ripple time is 12μs
(999999 to 000000). Maximum count frequency is 7.5MHz.
RESET
All 6 counter decades are reset to zero when Reset input is brought
low for a minimum of 4μs. The Overflow flip-flop is reset at the
same time. Reset must be high for a minimum of 1μs before next
valid count can be recorded.
SCAN OSCILLATOR AND COUNTER
The scan counter is driven by an internal oscillator whose
frequency is determined by a capacitor connected between
Oscillator input and Scan input. An external scan clock applied
to Scan input can also drive the scan counter. Scan counter
advances on negative edge of scan clock.
The counter scans from MSD to LSD. When Scan Reset input is
brought high the scan counter is forced to MSD state. Internal
synchonization guarantees proper scanning no matter when Scan
Reset is brought low relative to scan clock. Maximum scan
frequency is 500kHz.
DECIMAL POINT
A high at the Decimal Point input resets the Blanking flip-flop
causing the display to unblank. Decimal Point should be brought
high at start of digit time which has active Decimal Point.
7031-121102-1
December 2002
LSI/CSI
UL
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
LS7031
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
FIGURE 1
CONNECTION DIAGRAM - TOP VIEW
OSC. INPUT
SCAN INPUT
N.C.
B1/D1
B2/D1
N.C.
B4/D1
B8/D1
N.C.
B1/D2
B2/D2
B4/D2
V
SS
V
GG
N.C.
N.C.
V
DD
RESET COUNTER INPUT
LOAD LATCH INPUT
SCAN RESET INPUT
MSD STROBE 8
STROBE 7
STROBE 6
STROBE 5
STROBE 4
STROBE 3
STROBE 2
LSD STROBE 1
DECIMAL POINT INPUT
BLANK OUTPUT
OVERFLOW OUTPUT
OVERFLOW INPUT
DECADE 8 OUTPUT, D8
DECADE 7 OUTPUT, D7
DECADE 6 OUTPUT, D6
B8
B4
B2
B1
BCD
DATA
OUTPUTS
DIGIT
STROBE
OUTPUTS
LS7031
INPUT TO
DECADE 1
LATCH
INPUT TO
DECADE 2
LATCH
B8/D2
DIGIT STROBES
Timing of Digit Strobes is arranged such that both edges of strobe
are guardbanded by a minimum 400ns within valid BCD data when
scan frequency is 100kHz or less. The guardband is a minimum of
200ns at 250kHz scan frequency. At 500kHz only negative edge of
Strobe is guaranteed to be within valid BCD data by a minimum
200ns.
OVERFLOW
The Overflow flip-flop sets on the first negative transition of the Over-
flow Input and remains set until Reset is brought low. Data is trans-
ferred from Overflow flip-flop to Overflow Latch when Load is brought
low. A high at the Overflow Latch causes display to unblank. Over-
flow Output is output of Overflow Latch. MSB outputs of Decades
6, 7, 8 are available for use as Overflow Input.
LATCHES
Eight decades of latch are provided, two for storage of the two
external least significant decade counters and the remaining 6 for in-
ternal counter outputs. All latches when Load signal is brought low
for a minimum of 4μs and kept low until a minimum of 12μs has
elapsed from previous negative edge of count pulse (ripple time).
Storage of valid data occurs when Load signal is high for a minimum
of 1μs before next negative edge of count pulse or reset. Data is
transferred from Overflow flip-flop to Overflow latch at the same time.
A3800
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