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参数资料
| 型号： | LSP4301SAD |
| 厂商： | LITE-ON SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | 0.84 A SWITCHING CONTROLLER, 66 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封装： | SOP-8 |
| 文件页数： | 4/8页 |
| 文件大小： | 220K |
| 代理商： | LSP4301SAD |
Liteon Semiconductor Corporation
LSP4301
Low Power Off Line SMPS Primary Switcher
Rev1.0
4/8
DETAIL DESCRIPTIONS
1. Startup
This device includes a high voltage start up current source connected on the drain of the device. As soon as a voltage is
applied on the input of the converter, this start up current source is activated as long as VDD is lower than VDDon. When
reaching VDDon, the start up current source is switched off and the device begins to operate by turning on and off its main
power MOSFET. As the COMP pin does not receive any current from the optocoupler, the device operates at full current
capacity and the output voltage rises until reachingthe regulation point where the secondary loop begins to send a current
in the optocoupler. At this point, the converter enters a regulated operation where the COMP pin receives the amount of
current needed to deliver the right power on secondary side.
2. Feedback
A feedback pin controls the operation of the device. Unlike conventional PWM control circuits which use a voltage input
(the inverted input of an operational amplifier), the COMP pin is sensitive to current. Figure 9 presents the internal current
mode structure.
In a real application, the COMP pin is driven with an optocoupler which acts as a pull up. So, it is not possible to really
short this pin to ground and the above drain current value is not achievable. Nevertheless, the capacitor C is averaging the
voltage on the COMP pin, and when the optocoupler is off (start up or short circuit), it can be assumed that the
corresponding voltage is very close to 0 V.
3. Leading Edge Blanking(LEB)
At the instant the internal sense FET is turned on,there usually exists a high current spike through the sense FET,caused
by the primary side capacitance and secondary side rectifier diode reverse recovery.Excessive voltage across the sense
resistor would lead to false feedback operation in the current mode PWM control.To counter this effect,the device employs
a leading edge blanking(LEB) circuit. This circuit inhibits the PWM comparator for a short time(typically 500ns)after the
sense FET is turned on.
4. Under Voltage Lock Out(UVLO)
Once fault condition occurs,switching is terminated and the sense FET remains off. This causes VDD to fall. When VDD
reaches the UVLO stop voltage 8V, the protection is reset and the internal high voltage current source charges the VDD
capacitor. When VDD reaches the UVLO start voltage 14.5V, the device resumes its normal operation, In this manner, the
auto-restart can alternately enable and disable the switching of the power sense FET until the fault condition is eliminated.
5. Thermal Shutdown(TSD)
The sense FET and the control IC are integrated in the same chip, making it easier for the control IC to detect the
temperature of the sense FET. when the temperature exceeds approximately 170 ,thermal shutdown is activated. The
℃
device turn off the sense FET and the high voltage current source charge VDD. The device will go back to work when the
lower threshold temperature about 145
is reached.
℃
6. Over Voltage Protection(OVP)
An overvoltage detector on the VDD pin allows the LSP4301 to reset itself when VDD exceeds VDDovp. Note that this
event is only latched for the time needed by VDD to reach VDDoff, and then the device resumes normal operation
automatically.
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