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参数资料
| 型号： | LST4046QOTD |
| 厂商： | LITE-ON SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, QCC16 |
| 封装： | 4 X 4 MM, QFN-16 |
| 文件页数： | 3/8页 |
| 文件大小： | 194K |
| 代理商： | LST4046QOTD |
Liteon Semiconductor Corporation
LST4046
R-type Touch Screen Controller
Rev1.0
3/8
DETAIL DESCRIPTIONS
Digital Interface
SERIAL INTERFACE
Figure 1 shows the typical operation of the serial interface of the LST4046. The serial clock provides the conversion
clock and also controls the transfer of information to and from the LST4046. One complete conversion can be
achieved with 24 DCLK cycles as described in Figure 1.
The first eight DCLK cycles are used to write the control word to the control register via the DIN pin. The control
register is updated in stages as each bit is clocked in. Then the converter enters the acquisition mode and, if
required, the internal switches are turned on. After the three DCLK cycles of acquisition, the control word is complete
and the converter enters conversion mode. At this point, track-and-hold goes into hold mode, the input signal is
sampled, and the BUSY output goes high (BUSY returns low on the next falling edge of DCLK).
The next 12 DCLK cycles are used to perform the conversion and to clock out the conversion result. A 13th DCLK
cycle is needed to allow the host processor to clock in the LSB. Three more DCLK cycles clock out the three trailing
zeros and complete the 24 DCLK transfer. The 24 DCLK cycles can be provided from a DSP or via three bursts of
eight clock cycles from a microcontroller.
18
1
8
11
10
9
8765
432
1
0
CS
DCLK
DIN
BUSY
SAMPLE
ADC Status
IDLE
CONVERSION
IDLE
MSB
Zero filled
H.Z.
7
6543
210
DOUT
Figure 1: Typical operation timing diagram.
8-Bit Conversion
The LST4046 can be set up to operate in an 8-bit mode rather than a 12-bit mode. This mode allows a faster
throughput rate to be achieved, assuming 8-bit resolution is sufficient. When using 8-bit mode, a conversion is
complete four clock cycles earlier than in 12-bit mode. This can be used with serial interfaces that provide 12 clock
transfers, or two conversions can be completed with three 8-clock transfers. The throughput rate increases by 25%
as a result of the shorter conversion cycle, but the conversion itself can occur at a faster clock rate because the
internal settling time of the LST4046 is not as critical, because settling to eight bits is all that is required. The clock
rate can be as much as 50% faster. The faster clock rate and fewer clock cycles combine to provide double the
conversion rate.
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