参数资料
型号: LT1010CDD#TRPBF
厂商: Linear Technology
文件页数: 18/20页
文件大小: 0K
描述: IC BUFFER HI-SPEED 150MA 8-DFN
标准包装: 2,500
放大器类型: 缓冲器
电路数: 1
转换速率: 75 V/µs
增益带宽积: 20MHz
电流 - 输入偏压: 500µA
电流 - 电源: 5mA
电流 - 输出 / 通道: 150mA
电压 - 电源,单路/双路(±): 4.5 V ~ 40 V,±2.25 V ~ 20 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 8-WFDFN 裸露焊盘
供应商设备封装: 8-DFN-EP(3x3)
包装: 带卷 (TR)
LT1010
7
1010fe
APPLICATIONS INFORMATION
General
These notes briefly describe the LT1010 and how it is
used;adetailedexplanationisgivenelsewhere.1Emphasis
here will be on practical suggestions that have resulted
from working extensively with the part over a wide range
of conditions. A number of applications are also outlined
that demonstrate the usefulness of the buffer beyond that
of driving a heavy load.
Design Concept
The schematic below describes the basic elements of the
bufferdesign.Theopampdrivestheoutputsinktransistor,
Q3, such that the collector current of the output follower,
Q2, never drops below the quiescent value (determined by
I1 and the area ratio of D1 and D2). As a result, the high
frequency response is essentially that of a simple follower
even when Q3 is supplying the load current. The internal
feedback loop is isolated from the effects of capacitive
loading by a small resistor in the output lead.
idealized buffer with the unloaded gain specified for the
LT1010. Otherwise, it has zero offset voltage, bias current
and output resistance. Its output also saturates to the
internal supply terminals.2
+
R1
D2
I2
D1
A1
Q3
INPUT
OUTPUT
V+
V
1010 AI01
BIAS
I1
Q1
Q2
The scheme is not perfect in that the rate of rise of sink
current is noticeably less than for source current. This
can be mitigated by connecting a resistor between the
bias terminal and V+, raising quiescent current. A feature
of the final design is that the output resistance is largely
independentofthefollowerquiescentcurrentortheoutput
load current. The output will also swing to the negative rail,
which is particularly useful with single supply operation.
Equivalent Circuit
Below 1MHz, the LT1010 is quite accurately represented
by the equivalent circuit shown here for both small- and
large-signal operation. The internal element, A1, is an
ROUT
R
R
R
′ = RSAT – ROUT
VSOS+
V+
V
OUTPUT
INPUT
IB
VOS
VSOS–
1010 AI02
+
A1
Loaded voltage gain can be determined from the unloaded
gain, AV, the output resistance, ROUT, and the load resis-
tance, RL, using:
AVL =
AVRL
ROUT +RL
Maximum positive output swing is given by:
VOUT+ =
(V+ – VSOS+)RL
RSAT +RL
The input swing required for this output is:
VIN+ = VOUT+ 1+
ROUT
RL
– VOS + VOS
where
VOS is the 100mV clipping specified for the satu-
ration measurements. Negative output swing and input
drive requirements are similarly determined.
Supply Bypass
The buffer is no more sensitive to supply bypassing than
slower op amps as far as stability is concerned. The
0.1F disc ceramic capacitors usually recommended for
op amps are certainly adequate for low frequency work.
As always, keeping the capacitor leads short and using
1R. J. Widlar, “Unique IC Buffer Enhances Op Amp Designs; Tames Fast Amplifiers,”
Linear Technology Corp. TP-1, April, 1984.
2See electrical characteristics section for guaranteed limits.
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