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| 型号： | LT1058SW#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 16/16页 |
| 文件大小： | 0K |
| 描述： | IC PREC OP-AMP JFET QUAD 16SOIC |
| 标准包装： | 1,000 |
| 放大器类型： | J-FET |
| 电路数： | 4 |
| 转换速率： | 13 V/µs |
| 增益带宽积： | 5MHz |
| 电流 - 输入偏压： | 7pA |
| 电压 - 输入偏移： | 250µV |
| 电流 - 电源： | 1.7mA |
| 电压 - 电源，单路/双路(±)： | ±10 V ~ 18 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SO |
| 包装： | 带卷 (TR) |
LT1057/LT1058
9
10578fd
Settling time is measured in a test circuit which can be
found in the LT1055/LT1056 data sheet and in Application
Note 10.
Achieving Picoampere/Microvolt Performance
In order to realize the picoampere/microvolt level accuracy
of the LT1057/LT1058, proper care must be exercised. For
example, leakage currents in circuitry external to the op
amp can significantly degrade performance. High quality
insulation should be used (e.g., TeflonTM, Kel-F); cleaning
of all insulating surfaces to remove fluxes and other resi-
dues will probably be required. Surface coating may be
necessary to provide a moisture barrier in high humidity
environments.
Board leakage can be minimized by encircling the input
circuitry with a guard ring operated at a potential close to
that of the inputs; in inverting configurations, the guard
ring should be tied to ground, in noninverting connections,
to the inverting input. Guarding both sides of the printed
circuit board is required. Bulk leakage reduction depends
on the guard ring width.
The LT1057/LT1058 have the lowest offset voltage of any
dualandquadJFETinputopampsavailabletoday.However,
theoffsetvoltageanditsdriftwithtimeandtemperatureare
still not as good as on the best bipolar amplifiers (because
the transconductance of FETs is considerably lower than
that of bipolar transistors). Conversely, this lower trans-
conductance is the main cause of the significantly faster
speed performance of FET input op amps.
Offset voltage also changes somewhat with temperature
cycling. The AM grades show a typical 40V hysteresis
(50V on the M grades) when cycled over the –55°C to
125°Ctemperaturerange.Temperaturecyclingfrom0°Cto
70°C has a negligible (less than 20V) hysteresis effect.
The offset voltage and drift performance are also affected
by packaging. In the plastic N package, the molding com-
pound is in direct contact with the chip, exerting pressure
on the surface. While NPN input transistors are largely
unaffected by this pressure, JFET device drift is degraded.
Consequently for best drift performance, as shown in the
Typical Performance Characteristics distribution plots, the
J or H packages are recommended.
In applications where speed and picoampere bias currents
are not necessary, Linear Technology offers the bipolar
input, pin compatible LT1013 and LT1014 dual and quad
op amps. These devices have significantly better DC
specifications than any JFET input device.
Phase Reversal Protection
Most industry standard JFET input single, dual and quad
op amps (e.g., LF156, LF351, LF353, LF411, LF412,
OP-15, OP-16, OP-215, TL084) exhibit phase reversal at
the output when the negative common mode limit at the
input is exceeded (i.e., below –12V with ±15V supplies).
The photos below show a ±16V sine wave input (A), the
response of an LF412A in the unity gain follower mode
(B), and the response of the LT1057/LT1058 (C).
The phase reversal of photo (B) can cause lock-up in servo
systems. The LT1057/LT1058 does not phase-reverse due
to a unique phase reversal protection circuit.
APPLICATIONS INFORMATION
All Photos 5V/Div Vertical Scale, 50s/Div Horizontal Scale
(A) ±16V Sine Wave Input
(B) LF412A Output
(C) LT1057/LT1058 Output
Teon is a trademark of DuPont.
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| LT1070CT#PBF | 功能描述:IC REG MULTI CONFIG ADJ TO220-5 RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:250 系列:- 类型:降压（降压） 输出类型:固定 输出数:1 输出电压:1.2V 输入电压:2.05 V ~ 6 V PWM 型:电压模式 频率 - 开关:2MHz 电流 - 输出:500mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:6-UFDFN 包装:带卷 (TR) 供应商设备封装:6-SON（1.45x1） 产品目录页面:1032 (CN2011-ZH PDF) 其它名称:296-25628-2 |
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