参数资料
型号: LT1107CN8-5
厂商: Linear Technology
文件页数: 12/16页
文件大小: 0K
描述: IC REG BUCK BST INV 5V 0.4A 8DIP
标准包装: 50
类型: 降压(降压),升压(升压),反相
输出类型: 固定
输出数: 1
输出电压: 5V
输入电压: 2 V ~ 30 V
频率 - 开关: 63kHz
电流 - 输出: 400mA
同步整流器:
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: 8-DIP(0.300",7.62mm)
包装: 管件
供应商设备封装: 8-PDIP
LT1107
A PPLICATI
S I FOR ATIO
Figure 7 details current limit circuitry. Sense transistor A1,
whose base and emitter are paralleled with power switch
Q2, is ratioed such that approximately 0.5% of Q2’s
collector current flows in Q1’s collector. This current is
passed through internal 80 ? resistor R1 and out through
the I LIM pin. The value of the external resistor connected
V IN
Q3
OSCILLATOR
R LIM
(EXTERNAL)
DRIVER
I LIM
R1
80 ?
(INTERNAL)
SW1
Q1
Q2
between I LIM and V IN sets the current limit. When suffi-
cient switch current flows to develop a V BE across R1 +
R LIM , Q3 turns on and injects current into the oscillator,
turning off the switch. Delay through this circuitry is
approximately 800ns. The current trip point becomes less
accurate for switch ON times less than 3 μ s. Resistor
values programming switch ON time for 800ns or less will
SW2
1107 F07
Figure 7. LT1107 Current Limit Circuitry
5V
cause spurious response in the switch circuitry although
the device will still maintain output regulation.
Using the Gain Block
The gain block (GB) on the LT1107 can be used as an error
V BAT
R1
1.25V
REF
SET
+
V IN
LT1107
AO
47k
TO
PROCESSOR
( )
V LB – 1.25V
35.1 μ A
amplifier, low-battery detector or linear post regulator.
The gain block itself is a very simple PNP input op amp with
an open collector NPN output. The negative input of the
gain block is tied internally to the 1.25V reference. The
positive input comes out on the SET pin.
R2
GND
R3
R1 =
V LB = BATTERY TRIP POINT
R2 = 33k
Arrangement of the gain block as a low-battery detector is
straightforward. Figure 8 shows hookup. R1 and R2 need
only be low enough in value so that the bias current of the
SET input does not cause large errors. 33k for R2 is
adequate. R3 can be added to introduce a small amount of
R3 = 1.6M
Figure 8. Setting Low-Battery Detector Trip Point
1107 F08
hysteresis. This will cause the gain block to “snap” when
the trip point is reached. Values in the 1M to 10M range are
L1
D1
V OUT
optimal. The addition of R3 will change the trip point,
however.
R3
270k
I LIM
V IN
R2
+
C1
( )( )
V OUT = R2 + 1 1.25V
OutputrippleoftheLT1107,normally50mVat5V OUT can
be reduced significantly by placing the gain block in front
of the FB input as shown in Figure 9. This effectively
reduces the comparator hysteresis by the gain of the gain
block. Output ripple can be reduced to just a few millivolts
using this technique. Ripple reduction works with step-
down or inverting modes as well. For this technique to be
V BAT
R1
AO SW1
LT1107
FB SET
GND SW2
R1
1107 F09
effective, output capacitor C1 must be large, so that each
switching cycle increases V OUT by only a few millivolts.
1000 μ F is a good starting value. C1 should be a low ESR
Figure 9. Output Ripple Reduction Using Gain Block
type as well.
1107fa
12
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