参数资料
型号: LT1185C
厂商: Linear Technology Corporation
元件分类: 基准电压源/电流源
英文描述: Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection
中文描述: 无电容,NMOS管,150mA的低压差稳压器的反向电流保护
文件页数: 9/16页
文件大小: 211K
代理商: LT1185C
9
LT1185
APPLICATIU
U
W
U
Figure 2. Proper Connection of Positive Sense Lead
Shutdown Techniques
The LT1185 can be shut down by open-circuiting the REF
pin. The current flowing into this pin must be less than
0.4
μ
A to guarantee shutdown. Figure 3 details several
ways to create the “open” condition, with various logic
levels. For variations on these schemes, simply remember
that the voltage on the REF pin is 2.4V negative with
respect to the ground pin.
Output Overshoot
Very high input voltage slew rate during start-up may
cause the LT1185 output to overshoot. Up to 20% over-
shoot could occur with input voltage ramp-up rate exceed-
ing 1V/
μ
s. This condition cannot occur with normal 50Hz
to 400Hz rectified AC inputs because parasitic resistance
and inductance will limit rate of rise even if the power
switch is closed at the peak of the AC line voltage. This
assumes that the switch is in the AC portion of the circuit.
If instead, a switch is placed directly in the regulator input
so that a large filter capacitor is precharged, fast input slew
rates will occur on switch closure. The output of the
regulator will slew at a rate set by current limit and output
capacitor size; dVdt = I
LIM
/C
OUT
. With I
LIM
= 3.6A and C
OUT
= 2.2
μ
F, the output will slew at 1.6V/
μ
s and overshoot can
occur. This overshoot can be reduced to a few hundred
millivolts or less by increasing the output capacitor to
10
μ
F and/or reducing current limit so that output slew rate
is held below 0.5V/
μ
s.
A second possibility for creating output overshoot is
recovery from an output short. Again, the output slews at
a rate set by current limit and output capacitance. To avoid
overshoot, the ratio I
LIM
/C
OUT
should be less than
0.5
×
10
6
. Remember that load capacitance can be added
to C
OUT
for this calculation. Many loads will have multiple
supply bypass capacitors that total more than C
OUT
.
+
R1*
2.37k
R2
REF
GND
FB
V
OUT
V
IN
LT1185
R
LIM
+
V
IN
V
OUT
LT1185 F02
LOAD
PARASITIC
LEAD RESISTANCES
– r
b
+
I
GND
r
a
*R1 SHOULD BE CONNECTED DIRECTLY TO GROUND LEAD, NOT TO THE LOAD,
SO THAT r
0
. THIS LIMITS THE OUTPUT VOLTAGE ERROR TO (I
)(r
b
).
ERRORS CREATED BY r
ARE MULTIPLIED BY (1 + R2/R1). NOTE THAT V
INCREASESWITH INCREASING GROUND PIN CURRENT. R2 SHOULD BE CONNECTED
DIRECTLY TO LOAD FOR REMOTE SENSING
相关PDF资料
PDF描述
LT1185CT 9-Bit Odd/Even Parity Generators/Checkers 14-SOIC 0 to 70
LT1185I 9-Bit Odd/Even Parity Generators/Checkers 14-SOIC 0 to 70
LT1185IT 9-Bit Odd/Even Parity Generators/Checkers 14-SOIC 0 to 70
LT1185M 9-Bit Odd/Even Parity Generators/Checkers 14-SOIC 0 to 70
LT1185MK 9-Bit Odd/Even Parity Generators/Checkers 14-SOIC 0 to 70
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