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| 型号： | LT1247CS8#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/12页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR ISO PWM CM 8-SOIC |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 100% |
| 电源电压： | 8.2 V ~ 25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | 0°C ~ 100°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
LT1246/LT1247
A PPLICATI
S I FOR ATIO
ing conditions (V FB = 2.5V). The blanking time goes to zero
as the feedback pin is pulled to 0V. This means that the
blanking time will be minimized during start-up and also
during an output short-circuit fault. This blanking circuit
eliminates the need for an input filter at the current sense
input except in extreme cases. Eliminating the filter allows
the current sense loop to operate with minimum delays,
reducing peak currents during fault conditions.
Undervoltage Lockout
The LT1246/LT1247 incorporate an undervoltage lockout
comparator which prevents the internal reference circuitry
and the output from starting up until the supply voltage
reaches the start-up threshold voltage. The quiescent
current, below the start-up threshold, has been reduced to
less than 250 μ A (170 μ A typ.). This minimizes the power
loss due to the start-up resistor used in off-line converters.
In undervoltage lockout both V REF (pin 8) and the Output
(pin 6) are actively pulled low by Darlington connected
PNP transistors. They are designed to sink a few milliamps
of current and will pull down to about 1V. The pull-down
transistor at the reference pin can be used to reset the
external soft start capacitor. The pull-down transistor at
the output eliminates the external pull-down resistor re-
quired, with earlier devices, to hold the external MOSFET
gate low during undervoltage lockout.
Output
The LT1246/LT1247 incorporate a single high current
totem pole output stage. This output stage is capable of
driving up to ± 1A of output current. Cross-conduction
current spikes in the output totem pole have been elimi-
nated. These devices are primarily intended for driving
MOSFET switches. Rise time is typically 30ns and fall time
is typically 20ns when driving a 1.0nF load. A clamp is built
into the device to prevent the output from rising above 18V
in order to protect the gate of the MOSFET switch. The
output is actively pulled low during undervoltage lockout
by a Darlington PNP. This PNP is designed to sink several
milliamps and will pull the output down to approximately
1V. This active pull-down eliminates the need for the
external resistor which was required in older designs.
The output pin of the device connects directly to the
emitter of the upper NPN drive transistor and the collector
of the lower NPN drive transistor in the totem pole. The
collector of the lower transistor, which is n-type silicon,
forms a p-n junction with the substrate of the device. The
substate of the device is tied to ground. This junction is
reverse biased during normal operation. In some applica-
tions the parasitic LC of the external MOSFET gate can ring
and pull the output pin below ground. If the output pin is
pulled negative by more than a diode drop, the parasitic
diode formed by the collector of the output NPN and the
substrate will turn on. This can cause erratic operation of
the device. In these cases a Schottky clamp diode is
recommended from output to ground.
Reference
The internal reference of the LT1246/LT1247 is a 5V
Bandgap reference, trimmed to within ± 1% initial toler-
ance. The reference is used to power the majority of the
internal logic and the oscillator circuitry. The oscillator
charging current is supplied from the reference. The
feedback pin voltage and the clamp level for the current
sense comparator are derived from the reference voltage.
The reference can supply up to 20mA of current to power
external circuitry. Note that using the reference in this
manner, as a voltage regulator, will significantly increase
the power dissipation in the device, which will reduce the
operating ambient temperature range.
Design/Layout Considerations
LT1246/LT1247 are high speed circuits capable of gener-
ating pulsed output drive currents of up to 1A peak. The
rise and fall time for the output drive current is in the range
of 10ns to 20ns. High Speed circuit layout techniques
must be used to insure proper operation of the devices. Do
not attempt to use Proto-boards or wire-wrap tech-
niques to breadboard high speed switching regulator
circuits. They will not work properly.
Printed circuit layouts should include separate ground
paths for the voltage feedback network, oscillator capaci-
tor, and switch drive current. These ground paths should
be connected together directly at the ground pin (pin 5) of
the LT1246/LT1247. This will minimize noise problems
due to pulsed ground pin currents. V CC should be by-
passed, with a minimum of 0.1 μ F, as close to the device
as possible. High current paths should be kept short and
they should be separated from the feedback voltage net-
work with shield traces if possible.
9
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LT1248 | 制造商:LINER 制造商全称:Linear Technology 功能描述:Power Factor Controller |
| LT1248C | 制造商:LINER 制造商全称:Linear Technology 功能描述:Power Factor Controller |
| LT1248CN | 功能描述:IC PFC CTRLR AVERAGE CURR 16DIP RoHS:否 类别:集成电路 (IC) >> PMIC - PFC（功率因数修正） 系列:- 产品培训模块:GreenChip Synchronous Rectification Control Family of ICs 标准包装:1 系列:- 模式:间歇导电（DCM） 频率 - 开关:- 电流 - 启动:- 电源电压:8.6 V ~ 38 V 工作温度:-20°C ~ 150°C 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SO 包装:Digi-Reel® 其它名称:568-5348-6 |
| LT1248CN#PBF | 功能描述:IC PFC CTRLR AVERAGE CURR 16DIP RoHS:是 类别:集成电路 (IC) >> PMIC - PFC（功率因数修正） 系列:- 产品培训模块:GreenChip Synchronous Rectification Control Family of ICs 标准包装:1 系列:- 模式:间歇导电（DCM） 频率 - 开关:- 电流 - 启动:- 电源电压:8.6 V ~ 38 V 工作温度:-20°C ~ 150°C 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SO 包装:Digi-Reel® 其它名称:568-5348-6 |
| LT1248CN#PBF | 制造商:Linear Technology 功能描述:IC PFC CURRENT MODE 25V DI 制造商:Linear Technology 功能描述:IC, PFC, CURRENT MODE, 25V, DIP-16 |
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