参数资料
型号: LT1306ES8#TRPBF
厂商: Linear Technology
文件页数: 11/16页
文件大小: 0K
描述: IC REG BOOST 5V 1A 8SOIC
标准包装: 2,500
类型: 升压(升压)
输出类型: 固定
输出数: 1
输出电压: 5V
输入电压: 1.8 V ~ 7 V
PWM 型: 电流模式,混合
频率 - 开关: 310kHz
电流 - 输出: 1A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
供应商设备封装: 8-SOIC
LT1306
APPLICATIO N S I N FOR M ATIO N
R L = Maximum Load =
C Z =
where
Output Voltage
Maximum DC Load Current
D MAX = Maximum Converter Duty Cycle
The low frequency zero 1/R3C Z of the compensation
network is placed at ω P /2.
2
R 3 ω P
=
V O – V IN(MIN) + 0 .5
V O + 0 . 1
The capacitor C P ensures adequate gain margin beyond
the RHP zero. The high frequency pole 1/R3C P of the
amplifier frequency response is placed beyond ω Z .
There is also a second pole at the current loop crossover
frequency ω C (Figure 6). ω Z is much lower in frequency
than ω C . The loop is compensated by adjusting the midband
C P =
1
3 ω Z R 3
gain with resistor R3 (Figure 7) so that the overall loop gain
crosses 0dB before the minimum frequency RHP zero
(i.e., corresponding to the highest duty ratio). The value of
R3 can be estimated with the fromula:
Higher output filter capacitance rolls off the gain response
from a lower corner frequency so higher midband gain is
required in the compensation network to make the overall
loop gain cross 0dB just below ω Z .
R 3 =
390 V O (1 – D MAX )C O R L
L
Layout Consideration
To minimize EMI and high frequency resonances, it is
Due to the low transconductance of the error amplifier, the
gain setting resistor R3 is AC-coupled with capacitor C Z .
This prevents R3 from inducing an offset to the input of the
error amplifier. It also creates a pole at DC and a low
frequency zero.
The amplitude response of the error amplifier with the
compensation network shown is:
essential to keep the SW and the CAP trace leads as short
as possible. The input and the output bypass capacitors
C IN and C OUT should be placed close to the IC package and
soldered to the ground plane. A ground plane under the
switching regulator is highly recommended. Figure 8
shows a suggested component placement and PC board
layout.
V C ? R 2 ? 1 + ( S ? R 3 ? C Z )
[ (
= g m ? ?
?
V O ? R 1 + R 2 ? S ? C Z 1 + S ? R 3 ? C P
C Z >> C P
) ]
11
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