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参数资料
| 型号： | LT1339CN |
| 厂商： | Linear Technology |
| 文件页数： | 7/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST PWM CM 20-DIP |
| 标准包装： | 18 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 150kHz |
| 占空比： | 90% |
| 电源电压： | 最高 60V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 20-DIP（0.300"，7.62mm） |
| 包装： | 管件 |
LT1339
PI N FU N CTIO N S
SYNC (Pin 1): Oscillator Synchronization Pin with TTL-
Level Compatible Input. Input drives internal rising edge
triggered one-shot; sync signal on/off times should be
≥ 1 μ s (10% to 90% DC at 100kHz). Does not contain
internal pull-up. Connect to SGND if not used.
5V REF (Pin 2): 5V Output Reference. Allows connection
of external loads up to 10mA DC. (Reference is not
available in shutdown.) Typically bypassed with 1 μ F
capacitor to SGND.
CT (Pin 3): Oscillator Timing Pin. Connect a capacitor
(C CT ) to ground and a pull-up resistor (R CT ) to the 5V REF
supply. Typical values are CT = 1000pF and 10k ≤ R CT
≤ 30k.
SL/ADJ (Pin 4): Slope Compensation Adjustment.
Allows increased slope compensation for certain high
duty cycle applications. Resistive loading of the pin
increases effective slope compensation. A resistor
divider from the 5V REF pin can tailor the onset of addi-
tional slope compensation to specific regions in each
switch cycle. Pin can be floated or connected to 5V REF if
no additional slope compensation is required. (See
Applications Information section for slope compensa-
tion details.)
I AVG (Pin 5): Average Current Limit Integration. Fre-
quency response characteristic is set using the 50k ?
output impedance and external capacitor to ground.
Averaging roll-off typically set at 1 to 2 orders of magni-
tude under switching frequency. (Typical capacitor value
~1000pF for f O = 100kHz.) Shorting this pin to SGND will
disable the average current limit function.
SS (Pin 6): Soft Start. Generates ramping threshold for
regulator current limit during start-up and after UVLO
event by sourcing about 8 μ A into an external capacitor.
V C (Pin 7): Error Amplifier Output. RC load creates
dominant compensation in power supply regulation feed-
back loop to provide optimum transient response. (See
Applications Information section for compensation de-
tails.)
SGND (Pin 8): Small-Signal Ground. Connect to negative
terminal of C OUT .
V FB (Pin 9): Error Amplifier Inverting Input. Used as
voltage feedback input node for regulator loop. Pin
sources about 0.5 μ A DC bias current to protect from an
V REF (Pin 10): Bandgap Generated Voltage Reference
Decoupling. Connect a capacitor to signal ground. (Typi-
cal capacitor value ~0.1 μ F.)
SENSE + (Pin 11): Current Sense Amplifier Inverting
Input. Connect to most positive (DC) terminal of current
sense resistor.
SENSE – (Pin 12): Current Sense Amplifier Noninverting
Input. Connect to most negative (DC) terminal of current
sense resistor.
RUN/SHDN (Pin 13): Precision Referenced Shutdown.
Can be used as logic level input for shutdown control or
as an analog monitor for input supply undervoltage
protection, etc. IC is enabled when RUN/SHDN pin rising
edge exceeds 1.25V. About 25mV of hysteresis helps
assure stable mode switching. All internal functions are
disabled in shutdown mode. If this function is not
desired, connect RUN/SHDN to 12V IN (typically through
a 100k resistor). See Applications Information section.
PHASE (Pin 14): Output Driver Phase Control. If Pin 14
is not connected (floating), the topside driver operates
the main switch, with the bottom side driver operating
the synchronous switch. Shorting Pin 14 to ground
reverses the roles of the output drivers. PHASE is typi-
cally shorted to ground for inverting and boost configu-
rations. Positive buck configuration requires the PHASE
pin to float. See Applications Information section.
PGND (Pin 15): Power Ground. References the bottom
side output switch and internal driver control circuits.
Connect with low impedance trace to V IN decoupling
capacitor negative (ground) terminal.
BG (Pin 16): Bottom Side Output Driver. Connects to gate
of bottom side external power FET.
12V IN (Pin 17): 12V Power Supply Input. Bypass with at
least 1 μ F to PGND.
TS (Pin 18): Boost Output Driver Reference. Typically
connects to source of topside external power FET and
inductive switch node.
TG (Pin 19): Topside (Boost) Output Driver. Connects to
gate of topside external power FET.
V BOOST (Pin 20): Topside Power Supply. Bootstrapped
via 1 μ F capacitor tied to switch node (Pin 18) and
Schottky diode connected to the 12V IN supply.
open feedback path condition.
sn1339 1339fas
7
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LT1339CN#PBF | 功能描述:IC REG CTRLR BST PWM CM 20-DIP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,000 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:1MHz 占空比:50% 电源电压:9 V ~ 10 V 降压:无 升压:是 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:8-TSSOP（0.173"，4.40mm 宽） 包装:带卷 (TR) |
| LT1339CN#PBF | 制造商:Linear Technology 功能描述:DC-DC CONTROLLER CURRENT MODE 制造商:Linear Technology 功能描述:DC-DC CONTROLLER, CURRENT MODE, 150KHZ, |
| LT1339CSW | 功能描述:IC REG CTRLR BST PWM CM 20-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| LT1339CSW#PBF | 功能描述:IC REG CTRLR BST PWM CM 20-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,000 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:1MHz 占空比:50% 电源电压:9 V ~ 10 V 降压:无 升压:是 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:8-TSSOP（0.173"，4.40mm 宽） 包装:带卷 (TR) |
| LT1339CSW#TR | 功能描述:IC REG CTRLR BST PWM CM 20-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
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