参数资料
型号: LT1374IT7-5#PBF
厂商: Linear Technology
文件页数: 21/32页
文件大小: 0K
描述: IC REG BUCK 5V 4.5A TO220-7
标准包装: 50
类型: 降压(降压)
输出类型: 固定
输出数: 1
输出电压: 5V
输入电压: 5 V ~ 25 V
PWM 型: 电流模式
频率 - 开关: 500kHz
电流 - 输出: 4.5A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 通孔
封装/外壳: TO-220-7 成形引线
包装: 管件
供应商设备封装: TO-220-7
LT1374
APPLICATIO N S I N FOR M ATIO N
THERMAL CALCULATIONS
Power dissipation in the LT1374 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
Switch loss:
Boost current loss:
Thermal resistance for LT1374 package is influenced by
the presence of internal or backside planes. With a full
plane under the 16-lead TSSOP package, thermal resis-
tance will be about 40 ° C/W. To calculate die temperature,
use the proper thermal resistance number for the desired
package and add in worst-case ambient temperature:
T J = T A + θ JA (P TOT )
With the TSSOP16 package ( θ JA = 40 ° C/W), at an ambient
temperature of 50 ° C,
T J = 50 + 40 (0.87) = 85 ° C
For the DD package with a good copper plane under the
device, thermal resistance will be about 30 ° C/W. For the
conditions above:
T J = 50 + 30 (0.87) = 76 ° C
Die temperature is highest at low input voltage, so use
lowest continuous input operating voltage for thermal
calculations.
Quiescent current loss:
FREQUENCY COMPENSATION
Loop frequency compensation of switching regulators
canbearathercomplicatedproblembecausethereactive
R SW = Switch resistance ( ≈ 0.07)
24ns = Equivalent switch current/voltage overlap time
f = Switch frequency
Example: with V IN = 10V, V OUT = 5V and I OUT = 3A:
components used to achieve high efficiency also intro-
duce multiple poles into the feedback loop. The inductor
and output capacitor on a conventional step-down con-
verter actually form a resonant tank circuit that can exhibit
peaking and a rapid 180 ° phase shift at the resonant
frequency. By contrast, the LT1374 uses a “current mode”
architecture to help alleviate phase shift created by the
inductor. The basic connections are shown in Figure 9.
Figure 10 shows a Bode plot of the phase and gain of the
power section of the LT1374, measured from the V C pin to
the output. Gain is set by the 5.3A/V transconductance of
the LT1374 power section and the effective complex
impedance from output to ground. Gain rolls off smoothly
above the 600Hz pole frequency set by the 100μF output
capacitor. Phase drop is limited to about 70 ° . Phase
recovers and gain levels off at the zero frequency ( ≈ 16kHz)
set by capacitor ESR (0.1 ? ).
Total power dissipation is 0.68 + 0.15 + 0.04 = 0.87W.
1374fd
21
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