参数资料
型号: LT1376HVCS8
厂商: Linear Technology
文件页数: 23/28页
文件大小: 0K
描述: IC REG BUCK ADJ 1.5A 8SOIC
标准包装: 100
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 2.42 V ~ 21.5 V
输入电压: 5 V ~ 25 V
PWM 型: 电流模式
频率 - 开关: 500kHz
电流 - 输出: 1.5A
同步整流器:
工作温度: 0°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 管件
供应商设备封装: 8-SOIC
产品目录页面: 1327 (CN2011-ZH PDF)
LT1375/LT1376
APPLICATIO N S I N FOR M ATIO N
Keep in mind that this procedure does not take initial
Quiescent current loss:
( )
? V OUT ? 0 . 002
component tolerance into account. You should see fairly
clean response under all load and line conditions to ensure
that component variations will not cause problems. One
note here: according to Murphy, the component most
P Q = V IN ( 0 . 001 ) + V OUT
( 0 . 005 ) +
? 2 ?
? ?
V IN
likely to be changed in production is the output capacitor,
because that is the component most likely to have manu-
facturer variations (in ESR) large enough to cause prob-
lems. It would be a wise move to lock down the sources of
the output capacitor in production.
R SW = Switch resistance ( ≈ 0.4)
16ns = Equivalent switch current/voltage overlap time
f = Switch frequency
Example: with V IN = 10V, V OUT = 5V and I OUT = 1A:
( 0 . 4 )( 1 ) ( 5 ) + ? 16 ? 10 ? ( 1 )( 10 ) ? 500 ? 10
? ? ?
Apossibleexceptiontothe“cleanresponse”ruleisatvery
light loads, as evidenced in Figure 17 with I LOAD = 50mA.
Switching regulators tend to have dramatic shifts in loop
P SW
=
10
2
? 9
3 ?
?
( 5 ) ( 0 . 008 + 1 / 75 ) = 0 . 053 W
( ) ( ) = 0 . 04 W
= 10 ( ) + 5 ( ) +
responseatverylightloads,mostlybecausetheinductor
current becomes discontinuous. One common result is
very slow but stable characteristics. A second possibility
is low phase margin, as evidenced by ringing at the output
with transients. The good news is that the low phase
margin at light loads is not particularly sensitive to com-
ponent variation, so if it looks reasonable under a transient
test, it will probably not be a problem in production. Note
that frequency of the light load ringing may vary with
component tolerance but phase margin generally hangs in
there.
THERMAL CALCULATIONS
Power dissipation in the LT1376 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
Switch loss:
= 0 . 2 + 0 . 08 = 0 . 28 W
2
P BOOST =
10
2
5 0 . 002
P Q 0 . 001 0 . 005
10
Total power dissipation is 0.28 + 0.053 + 0.04 = 0.37W.
Thermal resistance for LT1376 package is influenced by
the presence of internal or backside planes. With a full
plane under the SO package, thermal resistance will be
about 120 ° C/W. No plane will increase resistance to about
160 ° C/W. To calculate die temperature, use the proper
thermal resistance number for the desired package and
add in worst-case ambient temperature:
T J = T A + θ JA (P TOT )
With the SO-8 package ( θ JA = 120 ° C/W), at an ambient
temperature of 70 ° C,
T J = 70 + 120 (0.37) = 114.4 ° C
( ) ( ) + 16 ns ( )( )( ) f
I V
V
P SW =
2
R SW I OUT V OUT
IN
OUT IN
Die temperature is highest at low input voltage, so use
lowest continuous input operating voltage for thermal
calculations.
Boost current loss:
( )
V OUT 0 . 008 + I OUT / 75
P BOOST =
2
V IN
13756fd
23
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