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参数资料
| 型号： | LT1376IN8-5#TR |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | 3 A SWITCHING REGULATOR, 570 kHz SWITCHING FREQ-MAX, PDIP8 |
| 封装： | 0.300 INCH, PLASTIC, DIP-8 |
| 文件页数： | 13/28页 |
| 文件大小： | 500K |
| 代理商： | LT1376IN8-5#TR |
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20
LT1375/LT1376
13756fd
APPLICATIONS INFORMATION
WU
U
Error amplifier transconductance phase and gain are shown
in Figure 14. The error amplifier can be modeled as a
transconductance of 2000
Mho, with an output imped-
ance of 200k
in parallel with 12pF. In all practical
applications, the compensation network from VC pin to
ground has a much lower impedance than the output
impedance of the amplifier at frequencies above 500Hz.
This means that the error amplifier characteristics them-
selves do not contribute excess phase shift to the loop, and
the phase/gain characteristics of the error amplifier sec-
tion are completely controlled by the external compensa-
tion network.
In Figure 15, full loop phase/gain characteristics are
shown with a compensation capacitor of 0.0033
F, giving
the error amplifier a pole at 240Hz, with phase rolling off
to 90
° and staying there. The overall loop has a gain of
introduce multiple poles into the feedback loop. The
inductor and output capacitor on a conventional step-
down converter actually form a resonant tank circuit that
can exhibit peaking and a rapid 180
° phase shift at the
resonant frequency. By contrast, the LT1376 uses a “cur-
rent mode” architecture to help alleviate phase shift cre-
ated by the inductor. The basic connections are shown in
Figure 12. Figure 13 shows a Bode plot of the phase and
gain of the power section of the LT1376, measured from
the VC pin to the output. Gain is set by the 2A/V transcon-
ductance of the LT1376 power section and the effective
complex impedance from output to ground. Gain rolls off
smoothly above the 100Hz pole frequency set by the
100
F output capacitor. Phase drop is limited to about
85
°. Phase recovers and gain levels off at the zero fre-
quency (
≈16kHz) set by capacitor ESR (0.1).
Figure 13. Response from VC Pin to Output
Figure 15. Overall Loop Characteristics
FREQUENCY (Hz)
GAIN:
V
C
PIN
TO
OUTPUT
(dB)
PHASE:
V
C PIN
TO
OUTPUT
(DEG)
40
20
0
–20
–40
40
0
–40
–80
–120
10
1k
10k
1M
1375/76 F13
100
100k
GAIN
PHASE
VIN = 10V
VOUT = 5V
IOUT = 500mA
FREQUENCY (Hz)
LOOP
GAIN
(dB)
LOOP
PHASE
(DEG)
80
60
40
20
0
–20
200
150
100
50
0
–50
10
1k
10k
1M
1375/76 F15
100
100k
GAIN
PHASE
VIN = 10V
VOUT = 5V, IOUT = 500mA
COUT = 100F, 10V, AVX TPS
CC = 3.3nF, RC = 0, L = 10H
Figure 12. Model for Loop Response
Figure 14. Error Amplifier Gain and Phase
–
+
2.42V
VSW
VC
LT1375
LT1376
GND
1375/76 F12
R1
OUTPUT
ESR
CF
CC
RC
ERROR
AMPLIFIER
FB
+
R2
C1
CURRENT MODE
POWER STAGE
gm = 2A/V
FREQUENCY (Hz)
GAIN
(
Mho)
PHASE
(DEG)
3000
2500
2000
1500
1000
500
200
150
100
50
0
–50
100
10k
100k
10M
1375/76 F14
1k
1M
GAIN
PHASE
ROUT
200k
COUT
12pF
VC
ERROR AMPLIFIER EQUIVALENT CIRCUIT
RLOAD = 50
VFB 2 10
–3
)
(
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