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| 型号： | LT1377IS8#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 10/12页 |
| 文件大小： | 0K |
| 描述： | IC REG MULTI CONFIG ADJ 8SOIC |
| 标准包装： | 100 |
| 类型： | 降压（降压），升压（升压），反相，Cuk，回扫，正向转换器 |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.25 V ~ 35 V |
| 输入电压： | 2.7 V ~ 25 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 1.5A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 管件 |
| 供应商设备封装： | 8-SOIC |
| 产品目录页面： | 1327 (CN2011-ZH PDF) |
LT1372/LT1377
APPLICATIO S I FOR ATIO
Frequency Compensation
Loop frequency compensation is performed on the output
of the error amplifier (V C pin) with a series RC network.
The main pole is formed by the series capacitor and the
output impedance ( ≈ 500k ? ) of the error amplifier. The
pole falls in the range of 2Hz to 20Hz. The series resistor
creates a “zero” at 1kHz to 5kHz, which improves loop
stability and transient response. A second capacitor,
typically one-tenth the size of the main compensation
capacitor, is sometimes used to reduce the switching
frequency ripple on the V C pin. V C pin ripple is caused by
output voltage ripple attenuated by the output divider and
(magnetic) radiation is minimized by keeping output di-
ode, switch pin, and output bypass capacitor leads as
short as possible. E field radiation is kept low by minimiz-
ing the length and area of all traces connected to the switch
pin. A ground plane should always be used under the
switcher circuitry to prevent interplane coupling.
The high speed switching current path is shown schemati-
cally in Figure 3. Minimum lead length in this path is
essential to ensure clean switching and low EMI. The path
including the switch, output diode, and output capacitor is
the only one containing nanosecond rise and fall times.
Keep this path as short as possible.
multiplied by the error amplifier. Without the second
capacitor, V C pin ripple is:
L1
SWITCH
NODE
V OUT
V C Pin Ripple =
1 .245(V RIPPLE )(g m )(R C )
(V OUT )
V IN
HIGH
FREQUENCY
CIRCULATING
LOAD
PATH
V RIPPLE = Output ripple (V P–P )
g m = Error amplifier transconductance
( ≈ 1500 μ mho)
R C = Series resistor on V C pin
V OUT = DC output voltage
To prevent irregular switching, V C pin ripple should be
kept below 50mV P–P . Worst-case V C pin ripple occurs at
maximum output load current and will also be increased
if poor quality (high ESR) output capacitors are used. The
addition of a 0.0047 μ F capacitor on the V C pin reduces
switching frequency ripple to only a few millivolts. A low
value for R C will also reduce V C pin ripple, but loop phase
margin may be inadequate.
Switch Node Considerations
For maximum efficiency, switch rise and fall time are
made as short as possible. To prevent radiation and high
frequency resonance problems, proper layout of the com-
ponents connected to the switch node is essential. B field
10
LT1372 ? F03
Figure 3
More Help
For more detailed information on switching regulator
circuits, please see Application Note 19. Linear Technol-
ogy also offers a computer software program, SwitcherCAD,
to assist in designing switching converters. In addition,
our applications department is always ready to lend a
helping hand.
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