参数资料
型号: LT1460DCS8-10#TRPBF1460
厂商: LINEAR TECHNOLOGY CORP
元件分类: 基准电压源/电流源
英文描述: 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 10 V, PDSO8
封装: 0.150 INCH, LEAD FREE, PLASTIC, SOP-8
文件页数: 8/24页
文件大小: 509K
代理商: LT1460DCS8-10#TRPBF1460
LT1460
16
1460f
LT1460-5
RL
VOUT
VGEN
1460 F06
CIN
0.1
F
5V
4V
CL
VIN = 5V
2
s/DIV
5V
4V
RL = 10k
RL = 1k
1460 F07
VGEN
VOUT
10
s/DIV
5V
4V
RL = 10k
RL = 1k
1460 F08
VGEN
VOUT
APPLICATIO S I FOR ATIO
WU
U
RS = 2Ω and CL = 1F. RS should not be made arbitrarily
large because it will limit the load regulation.
Figure 6 to Figure 8 illustrate response in the LT1460-5.
The 1V step from 5V to 4V produces a current step of
1mA or 100A for RL = 1k or RL = 10k. Figure 7 shows
the response of the reference with no load capacitance.
The reference settles to 5mV (0.1%) in less than 2s for
a 100A pulse and to 0.1% in 3s with a 1mA step. When
load capacitance is greater than 0.01F, the reference begins
to ring due to the pole formed with the output impedance.
Figure 8 shows the response of the reference to a 1mA
Figure 6. Response Time Test Circuit
Figure 8. CL = 0.01F
Figure 7. CL = 0
and 100A load current step with a 0.01F load capacitor.
Figure 9 to Figure 11 illustrate response of the LT1460-10.
The 1V step from 10V to 9V produces a current step of
1mA or 100A for RL = 1k or RL = 10k. Figure 10 shows
the response of the reference with no load capacitance.
The reference settles to 10mV (0.1%) in 0.4s for a 100A
pulse and to 0.1% in 0.8s with a 1mA step. When load
capacitance is greater than 0.01F, the reference begins
to ring due to the pole formed with the output impedance.
Figure 11 shows the response of the reference to a 1mA and
100A load current step with a 0.01F load capacitor.
Figure 11. CL = 0.01F
Figure 10. CL = 0
Figure 9. Response Time Test Circuit
LT1460-10
RL
VOUT
VGEN
1460 F09
CIN
0.1
F
10V
9V
CL
VIN = 12.5V
2
s/DIV
10V
9V
RL = 10k
RL = 1k
1460 F10
VGEN
VOUT
10
s/DIV
10V
9V
RL = 10k
RL = 1k
1460 F11
VGEN
VOUT
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