参数资料
型号: LT1507CS8-3.3#PBF
厂商: Linear Technology
文件页数: 18/20页
文件大小: 0K
描述: IC REG BUCK 3.3V 1.5A 8SOIC
标准包装: 100
类型: 降压(降压)
输出类型: 固定
输出数: 1
输出电压: 3.3V
输入电压: 4 V ~ 15 V
PWM 型: 电流模式
频率 - 开关: 500kHz
电流 - 输出: 1.5A
同步整流器:
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 管件
供应商设备封装: 8-SOIC
产品目录页面: 1327 (CN2011-ZH PDF)
LT1507
APPLICATIO N S I N FOR M ATIO N
Example: with V IN = 5V, V OUT = 3.3V, I OUT = 1A;
2.0
GAIN (A/V)
80
( ) ( )
( 0 . 4 )( 1 ) ( 3 . 3 ) ?
+ 16 10 ? 9 ? ( 1 )( 5 ) ? 500 10 3 ?
??
??
??
??
P SW =
P BOOST = ( 3 . 3 ) ? 0 . 008 +
= 0 . 046 W
2
5
= 0 . 26 + 0 . 04 = 0 . 3 W
2 ? 1 ?
?
5 ? 75 ?
P Q = 5 ( 0 . 003 ) + 3 . 3 ( 0 . 005 ) = 0 . 032 W
1.5
1.0
0.5
0
V OUT = 3.3V
I OUT = 250mA
V IN = 5V
L = 10 μ H
PHASE
40
0
–40
–80
Total power dissipation is 0.3 + 0.046 + 0.032 = 0.38W.
10
100
1k 10k
FREQUENCY (Hz)
100k
LT1507 ? F08
Thermal resistance for the LT1507 packages is influenced
by the presence of internal or backside planes. With a full
plane under the SO package, thermal resistance will be
about 120 ° C/W. No plane will increase resistance to about
150 ° C/W. To calculate die temperature, use the proper
thermal resistance number for the desired package and
add in worst-case ambient temperature;
T J = T A + θ JA (P TOT )
With the S8 package ( θ JA = 120 ° C/W) at an ambient
temperature of 70 ° C;
T J = 70 + 120(0.38) = 116 ° C
FREQUENCY COMPENSATION
The LT1507 uses a “current mode” architecture to help
alleviate phase shift created by the inductor. The basic
Figure 8. Phase and Gain from V C Pin Voltage
to Inductor Current
parallel with 12pF. In all practical applications, the com-
pensation network from V C pin to ground has a much
lower impedance than the output impedance of the ampli-
fier at frequencies above 500Hz. This means that the error
amplifier characteristics themselves do not contribute
excess phase shift to the loop and the phase/gain charac-
teristics of the error amplifier section are completely
controlled by the external compensation network.
The complete small-signal model is shown in Figure 9. R1
and R2 are the divider used to set output voltage. These are
internal on the fixed voltage LT1507-3.3 with R1 = 1.8k
and R2 = 5k. R C , C C and C F are external compensation
connections are shown in Figure 9. Gain of the power stage
can be modeled as 1.8A/V transconductance from the V C
POWER STAGE
g m = 1.8A/V
LT1507
V SW
L1
OUTPUT
pin voltage to current delivered to the output. This is
shown in Figure 8 where the transconductance from V C
12pF
ERROR AMPLIFIER
g m = 2000 μ ho
F B
R1
pin to inductor current is essentially flat from 50Hz to
50kHz and phase shift is minimal in the important loop
unity-gain band of 1kHz to 50kHz. Inductor variation from
3 μ H to 20 μ H will have very little effect on these curves.
Overall gain from the V C pin to output is then modeled as
the product of 1.8A/V transconductance multiplied by the
complex impedance of the load in parallel with the output
capacitor model.
200k
GND
C F
V C
R C
C C
2.42V
R2
ESR
+
C1
1507 ? F09
The error amplifier can be modeled as a transconductance
of 2000 μ mho, with an output impedance of 200k ? in
18
Figure 9. Small-Signal Model for Loop Stability Analysis
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