参数资料
型号: LT1507CS8-3.3#TRPBF
厂商: Linear Technology
文件页数: 17/20页
文件大小: 0K
描述: IC REG BUCK 3.3V 1.5A 8SOIC
标准包装: 2,500
类型: 降压(降压)
输出类型: 固定
输出数: 1
输出电压: 3.3V
输入电压: 4 V ~ 15 V
PWM 型: 电流模式
频率 - 开关: 500kHz
电流 - 输出: 1.5A
同步整流器:
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
供应商设备封装: 8-SOIC
LT1507
APPLICATIO N S I N FOR M ATIO N
V P-P ≥
( 6 . 6 ? 4 . 7 )( 1 ? 0 . 25 )
? ?
6 ? ? ? ?
? 6 ? ?
2 ? 1 10 ? ? 5 10 1 . 8
= 5 . 2 k
R S =
( ) ( )
0 . 09 ? 2 10 ? 9 ? ? 1 10 6 ?
C ≥
= 612 pF
R S = SYNC S S
works by prematurely tripping the oscillator before it
reaches its normal peak value. For instance, if the oscilla-
tor is synchronized at twice its nominal frequency, oscil-
lator amplitude will drop by half. A ramp which previously
started at the 40% point now starts at the 80% point! This
effectively blocks slope compensation and the regulator
may respond with fluctuating pulse widths, a “phase
oscillation” if you will. The regulator output stays in
regulation but subharmonic frequencies are generated at
the switch node.
The solution to this problem is to generate an external
ramp that replaces the missing internal ramp. As it turns
out, this is not difficult if the sync signal can be arranged
to have a fairly low duty cycle (< 35%). The ramp is created
by AC coupling a resistor from the sync signal to the
compensation capacitor as shown in Figure 7. This gener-
ates a negative ramp on the V C pin during switch ON time
that emulates the missing internally generated ramp.
Amplitude of the ramp should be about 100mV to 200mV
peak-to-peak. The formulas for calculating the values of
R S and C S are shown below. Note that the C S value is
unimportant as long as it exceeds the value given. The
formula assures that the impedance of C S will be small
compared to R S .
V ( DC )( 1 ? DC )
V P-P ( C C )( f )
For V IN = 4.7, V OUT = 3.3V, f = 1MHz, L = 5 μ H and DC S = 25%:
= 71 mV
?
? ? ? ? ? ? ? ?
To avoid small values of R S , the compensation capacitor (C C )
should be made as small as possible. 2000pF will work in
most situations. If we increase V PP to 90mV for a little
cushion, R S will be:
( 5 )( 0 . 25 )( 0 . 75 )
? ? ? ?
? ? ? ?
20
? ? ? ?
2 π ? 1 ( 10 6 ) ? ( 5200 )
THERMAL CALCULATIONS
Power dissipation in the LT1507 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current and input quiescent current. The formulas below
show how to calculate each of these losses. These formu-
las assume continuous mode operation, so they should
not be used for calculating efficiency at light load currents.
Switch loss:
R SW OUT OUT )
( I
) ( V
C S >
20
2 π ( f )( R S )
2
P SW = + 16 ns ( I OUT )( V IN )( f )
V IN
?
?
V
I
P BOOST = OUT ? 0 . 008 + OUT ?
V P-P ≥
V SYNC = Peak-to-peak value of sync signal
DC S = Duty cycle of incoming sync signal
V P-P = Desired amplitude of ramp
f = Sync frequency
Theoretical minimum amplitude for the ramp, assuming
no internal ramp, is:
( 2V OUT ? V IN )( 1 ? DC S )
2 ( f )( L )( g mP )
g mP = Transconductance from V C pin to switch current
(1.8A/V for the LT1507).
Boost current loss:
2
V IN ? 75 ?
Quiescent current loss:
P Q = V IN ( 0 . 003 ) + V OUT ( 0 . 005 )
R SW = Switch resistance ( ≈ 0.4 ? )
16ns = Equivalent switch current/voltage overlap time
f = Switching frequency
17
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