参数资料
型号: LT1640HCS8#PBF
厂商: Linear Technology
文件页数: 12/16页
文件大小: 192K
描述: IC CONTRLR HOTSWAP NEGVOLT 8SOIC
标准包装: 100
类型: 热交换控制器
应用: 通用
内部开关:
电源电压: -10 V ~ -80 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
12
LT1640L/LT1640H
1640lhfb
The new threshold voltage when the input moves from low
to high is:
V
V
R   R    R   R    R   R
R   R
UV LH
UVH
,
"
"
"
"
=
+
+
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
2   3    1   3    1   2
2   3
where V
UVH
 is typically 1.243V.
The new threshold voltage when the input moves from
high to low is:
 
V
V
R   R    R   R    R   R
R   R
V
R
R
UV HL
UVL
GATE
,
"
"
"
"

"
=
+
+
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
2   3    1   3    1   2
2   3
1
3
where V
UVL
 is typically 1.223V.
The new hysteresis value will be:
 
V
V
R   R    R   R    R   R
R   R
V
R
R
HYS
UVHY
GATE
=
+
+
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
+
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
2   3    1   3    1   2
2   3
1
3
"
"
"
"
"
With R1 = 562k, R2 = 16.9k and R3 = 1.62M, V
GATE
 = 13.5V
and V
UVHY
 = 20mV, the undervoltage threshold will be 43V
(from low to high) and 37.6V (from high to low). The
hysteresis is 5.4V. A separate resistor divider should be
used to set the overvoltage threshold given by:
APPLICATIONS INFORMATION
U
U
U
V
V
R    R
R
OV
OVH
=
+
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
4    5
5
With R4 = 506k, R5 = 8.87k and V
OVH
 = 1.223V, the
overvoltage threshold will be 71V.
PWRGD/PWRGD Output
The PWRGD/PWRGD output can be used to directly en-
able a power module when the input voltage to the module
is within tolerance. The LT1640L has a PWRGD output for
modules with an active low enable input, and the LT1640H
has a PWRGD output for modules with an active high
enable input.
When the DRAIN voltage of the LT1640H is high with
respect to V
EE
 (Figure 11), the internal transistor Q3 is
turned off and R7 and Q2 clamp the PWRGD pin one diode
drop (H0.7V) above the DRAIN pin. Transistor Q2 sinks
the modules pull-up current and the module turns off.
When the DRAIN voltage drops below V
PG
, Q3 will turn on,
shorting the bottom of R7 to DRAIN and turning Q2 off.
The pull-up current in the module then flows through R7,
pulling the PWRGD pin high and enabling the module.
+
V
EE
V
DD
LT1640H
SENSE
C1
C3
Q1
R2
R3
C2
R4
R5
R6
R1
4
3
2
OV
GND
48V
UV
5
6
8
1
7
GATE
1640 F11
PWRGD
DRAIN
V
EE
R7
6.5k
Q2

+
V
PG
Q3
ACTIVE HIGH
ENABLE MODULE
V
OUT
+
V
OUT

V
IN
+
V
IN

ON/OFF
GND
(SHORT PIN)
*
* DIODES INC. SMAT70A
2?1N4148
4
3
2
1
+

Figure 11. Active High Enable Module
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