参数资料
型号: LT1677IS8#PBF
厂商: Linear Technology
文件页数: 7/20页
文件大小: 0K
描述: IC OPAMP R-R I/O SGL LN 8SOIC
标准包装: 100
放大器类型: 通用
电路数: 1
输出类型: 满摆幅
转换速率: 2.5 V/µs
增益带宽积: 7.2MHz
电流 - 输入偏压: 2nA
电压 - 输入偏移: 20µV
电流 - 电源: 2.75mA
电流 - 输出 / 通道: 35mA
电压 - 电源,单路/双路(±): 3 V ~ 36 V,±1.5 V ~ 18 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SO
包装: 管件
15
LT1677
1677fa
TA = 25°C
VS = ±15V
RL CONNECTED TO 0V
MEASURED ON TEKTRONIX 577 CURVE TRACER
TA = 25°C
VS = 5V
RL = 600
MEASURED ON TEKTRONIX 577 CURVE TRACER
Rail-to-Rail Input
The LT1677 has the lowest voltage noise, offset voltage
and highest gain when compared to any rail-to-rail op
amp. The input common mode range for the LT1677 can
exceed the supplies by at least 100mV. As the common
mode voltage approaches the positive rail (+VS – 0.7V),
the tail current for the input pair (Q1, Q2) is reduced,
which prevents the input pair from saturating (refer to the
Simplified Schematic). The voltage drop across the load
resistors RC1, RC2 is reduced to less than 200mV, degrad-
ing the slew rate, bandwidth, voltage noise, offset voltage
and input bias current (the cancellation is shut off).
When the input common mode range goes below 1.5V
above the negative rail, the NPN input pair (Q1, Q2) shuts
off and the PNP input pair (Q8, Q9) turns on. The offset
voltage, input bias current, voltage noise and bandwidth
are also degraded. The graph of Offset Voltage Shift vs
Common Mode shows where the knees occur by display-
ing the change in offset voltage. The change-over points
are temperature dependent, see the graph Common Mode
Range vs Temperature.
APPLICATIO S I FOR ATIO
WU
UU
INPUT
VOLTAGE
(50
V/DIV)
0
5
10
15
–5
–10
–15
OUTPUT VOLTAGE (V)
RL = 600
Figure 9. Voltage Gain Split Supply
INPUT
VOLTAGE
(5
V/DIV)
34
2
1
0
OUTPUT VOLTAGE (V)
RL TO 5V
Figure 10. Voltage Gain Single Supply
RL TO 0V
5
Rail-to-Rail Output
The rail-to-rail output swing is achieved by using transis-
tor collectors (Q28, Q29) instead of customary class A-B
emitter followers for the output stage. Referring to the
Simplified Schematic, the output NPN transistor (Q29) sinks
the current necessary to move the output in the negative
direction. The change in Q29’s base emitter voltage is re-
flected directly to the gain node (collectors of Q20 and Q16).
For large sinking currents, the delta VBE of Q29 can domi-
nate the gain. Figure 9 shows the change in input voltage
for a change in output voltage for different load resistors
connected between the supplies. The gain is much higher
for output voltages above ground (Q28 sources current)
since the change in base emitter voltage of Q28 is attenu-
ated by the gain in the PNP portion of the output stage.
Therefore, for positive output swings (output sourcing
current) there is hardly any change in input voltage for any
load resistance. Highest gain and best linearity is achieved
when the output is sourcing current, which is the case in
single supply operation when the load is ground referenced.
Figure 10 shows gains for both sinking and sourcing load
currents for a worst-case load of 600
.
RL = 1k
RL = 10k
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