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参数资料
| 型号： | LT1683IG |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | Ultralow Noise Push-Pull DC/DC Controller |
| 中文描述： | SWITCHING CONTROLLER, 250 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封装： | 5.30 MM, PLASTIC, SSOP-20 |
| 文件页数： | 16/24页 |
| 文件大小： | 237K |
| 代理商： | LT1683IG |
16
LT1683
1683f
APPLICATIU
So if we wanted to turn on at 20V with 2V of hysteresis:
W
U
U
RA
V
V
A
V
20
V
V
V
k
RB
V
24
V
1 39
.
V
)
A
V
V
k
=
1 39
=
=
=
2
24
1 39
μ
20
20
0 1
23 4
2
0 1
1 75
.
1 39
.
(
μ
Resistor values could be altered further by adding Zeners
in the divider string. A resistor in series with SHDN pin
could further change hysteresis without changing turn on
voltage.
Frequency Compensation
Loop frequency compensation is accomplished by way of
a series RC network on the output of the error amplifier
(V
C
pin).
To prevent irregular switching, V
C
pin ripple should be
kept below 50mV
P-P
. Worst-case V
C
pin ripple occurs at
maximum output load current and will also be increased if
poor quality (high ESR) output capacitors are used. The
addition of a 0.0047
μ
F capacitor for C
VC2
pin reduces
switching frequency ripple to only a few millivolts. A low
value for R
VC
will also reduce V
C
pin ripple, but loop phase
margin may be inadequate.
Setting Current Limit
The sense resistor sets the value for maximum operating
current. When the CS pin voltage is 0.1V the gate drivers
will immediately go low (no slew control). Therefore the
sense resistor value should be set to R
S
= 0.1V/I
SW(PEAK)
,
where I
SW(PEAK)
is the peak current in the MOSFETs.
I
SW(PEAK)
will depend on the topology and component
values and tolerances. Certainly it should be set below the
saturation current value for the transformer.
If CS pin voltage is 0.22V in addition to the drivers going
low, V
C
and SS will be discharged to ground. This is to
provide additional protection in the event of a short circuit.
By discharging V
C
and SS the MOSFET will not be stressed
as hard on subsequent cycles since the current trip will be
set lower.
Turn off of the MOSFETs will normally be inhibited for
about 100ns at the start of every turn on cycle. This is to
prevent noise from interfering with normal operation of
the controller. This current sense blanking does not pre-
vent the outputs from be turned off in the event of a fault.
Slewing of the gate voltage effectively provides additional
blanking.
Traces to the SENSE resistor should be kept short and
wide to minimize resistance and inductance.
Soft-Start
The soft-start pin is used to provide control of switching
current during startup. The max voltage on the V
C
pin is
approximately the voltage on the SS pin. A current source
will linearly charge a capacitor on the SS pin. The V
C
pin
voltage will thus ramp also. The approximate time for the
voltage on these pins to ramp is (1.31V/9
μ
A) C
SS
or
approximately 146ms per
μ
F.
Figure 6
V
C
PIN
1683 F06
R
VC
2k
C
VC
0.01
μ
F
C
4.7nF
Referring to Figure 6, the main pole is formed by capacitor
C
VC
and the output impedance of the error amplifier
(approximately 400k
). The series resistor R
VC
creates a
“zero” which improves loop stability and transient re-
sponse. A second capacitor C
VC2
, typically one-tenth the
size of the main compensation capacitor, is sometimes
used to reduce the switching frequency ripple on the V
C
pin. V
C
pin ripple is caused by output voltage ripple
attenuated by the output divider and multiplied by the error
amplifier. Without the second capacitor, V
C
pin ripple is:
V
V
gm R
V
CPINRIPPLE
RIPPLE
VC
OUT
=
1 25
.
where V
RIPPLE
= Output ripple (V
P-P
)
gm = Error amplifier transconductance
R
VC
= Series resistor on V
C
pin
V
OUT
= DC output voltage
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