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| 型号： | LT1721CGN#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 6/28页 |
| 文件大小： | 0K |
| 描述： | IC COMP R-RINOUT QUAD 16-SSOP |
| 标准包装： | 2,500 |
| 系列： | UltraFast™ |
| 类型： | 通用 |
| 元件数： | 4 |
| 输出类型： | CMOS，满摆幅，TTL |
| 电压 - 电源，单路/双路(±)： | 2.7 V ~ 6 V |
| 电压 - 输入偏移（最小值）： | 3mV @ 5V |
| 电流 - 输入偏压（最小值）： | 6µA @ 5V |
| 电流 - 输出（标准）： | 20mA |
| 电流 - 静态（最大值）： | 7mA |
| CMRR, PSRR（标准）： | 70dB CMRR，80dB PSRR |
| 传输延迟（最大）： | 10ns |
| 磁滞： | 7mV |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 安装类型： | 表面贴装 |
| 包装： | 带卷 (TR) |
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LT1720/LT1721
14
17201fc
Speed Limits
The LT1720/LT1721 comparators are intended for high
speed applications, where it is important to understand a
few limitations. These limitations can roughly be divided
into three categories: input speed limits, output speed
limits, and internal speed limits.
There are no signicant input speed limits except the shunt
capacitance of the input nodes. If the 2pF typical input
nodes are driven, the LT1720/LT1721 will respond.
The output speed is constrained by two mechanisms,
the rst of which is the slew currents available from the
output transistors. To maintain low power quiescent op-
eration, the LT1720/LT1721 output transistors are sized
to deliver 25mA to 45mA typical slew currents. This is
sufcient to drive small capacitive loads and logic gate
inputs at extremely high speeds. But the slew rate will
slow dramatically with heavy capacitive loads. Because
the propagation delay (tPD) denition ends at the time the
output voltage is halfway between the supplies, the xed
slew current actually makes the LT1720/LT1721 faster at
3V than 5V with 20mV of input overdrive.
Another manifestation of this output speed limit is skew,
the difference between tPDLH and tPDHL. The slew currents
of the LT1720/LT1721 vary with the process variations of
the PNP and NPN transistors, for rising edges and falling
edges respectively. The typical 0.5ns skew can have either
polarity, rising edge or falling edge faster. Again, the skew
will increase dramatically with heavy capacitive loads.
The skews of comparators in a single package are corre-
lated, but not identical. Besides some random variability,
there is a small (100ps to 200ps) systematic skew due to
physical parasitics of the packages. For the LT1720 SO-8,
comparator A, whose output is adjacent to the VCC pin,
will have a relatively faster rising edge than comparator
B. Likewise, comparator B, by virtue of an output adjacent
to the ground pin will have a relatively faster falling edge.
Similar dependencies occur in the LT1721 S16, while the
systemic skews in the smaller MSOP and SSOP packages
are half again as small. Of course, if the capacitive loads on
the two comparators of a single package are not identical,
the differential timing will degrade further.
APPLICATIONS INFORMATION
The second output speed limit is the clamp turnaround.
The LT1720/LT1721 output is optimized for fast initial
response, with some loss of turnaround speed, limiting
the toggle frequency. The output transistors are idled in a
low power state once VOH or VOL is reached by detecting
the Schottky clamp action. It is only when the output has
slewed from the old voltage to the new voltage, and the
clamp circuitry has settled, that the idle state is reached
and the output is fully ready to transition again. This clamp
turnaround time is typically 8ns for each direction, resulting
in a maximum toggle frequency of 62.5MHz, or a 125MB
data rate. With higher frequencies, dropout and runt pulses
can occur. Increases in capacitive load will increase the time
needed for slewing due to the limited slew currents and
the maximum toggle frequency will decrease further. For
higher toggle frequency applications, refer to the LT1715,
whose output stage can toggle at 150MHz typical.
The internal speed limits manifest themselves as disper-
sion. All comparators have some degree of dispersion,
dened as a change in propagation delay versus input
overdrive. The propagation delay of the LT1720/LT1721
will vary with overdrive, from a typical of 4.5ns at 20mV
overdrive to 7ns at 5mV overdrive (typical). The LT1720/
LT1721’s primary source of dispersion is the hysteresis
stage. As a change of polarity arrives at the gain stage,
the positive feedback of the hysteresis stage subtracts
from the overdrive available. Only when enough time has
elapsed for a signal to propagate forward through the gain
stage, backwards through the hysteresis stage and forward
through the gain stage again, will the output stage receive
the same level of overdrive that it would have received in
the absence of hysteresis.
With 5mV of overdrive, the LT1720/LT1721 are faster with
a 5V supply than with a 3V supply, the opposite of what
is true with 20mV overdrive. This is due to the internal
speed limit, because the gain stage is faster at 5V than 3V
due primarily to the reduced junction capacitances with
higher reverse voltage bias.
In many applications, as shown in the following examples,
there is plenty of input overdrive. Even in applications
providing low levels of overdrive, the LT1720/LT1721
are fast enough that the absolute dispersion of 2.5ns
(= 7 – 4.5) is often small enough to ignore.
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相关代理商/技术参数 |
参数描述 |
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| LT1721CS | 功能描述:IC COMP R-RINOUT QUAD 16-SOIC RoHS:否 类别:集成电路 (IC) >> 线性 - 比较器 系列:UltraFast™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:通用 元件数:1 输出类型:CMOS，推挽式，满摆幅，TTL 电压 - 电源，单路/双路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 电压 - 输入偏移（最小值）:5mV @ 5.5V 电流 - 输入偏压（最小值）:1pA @ 5.5V 电流 - 输出（标准）:- 电流 - 静态（最大值）:24µA CMRR, PSRR（标准）:80dB CMRR，80dB PSRR 传输延迟（最大）:450ns 磁滞:±3mV 工作温度:-40°C ~ 85°C 封装/外壳:6-WFBGA，CSPBGA 安装类型:表面贴装 包装:管件 其它名称:Q3554586 |
| LT1721CS#PBF | 功能描述:IC COMP R-RINOUT QUAD 16-SOIC RoHS:是 类别:集成电路 (IC) >> 线性 - 比较器 系列:UltraFast™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:带电压基准 元件数:4 输出类型:开路漏极 电压 - 电源，单路/双路(±):2.5 V ~ 11 V，±1.25 V ~ 5.5 V 电压 - 输入偏移（最小值）:10mV @ 5V 电流 - 输入偏压（最小值）:- 电流 - 输出（标准）:0.015mA @ 5V 电流 - 静态（最大值）:8.5µA CMRR, PSRR（标准）:80dB CMRR，80dB PSRR 传输延迟（最大）:- 磁滞:- 工作温度:0°C ~ 70°C 封装/外壳:16-SOIC（0.154"，3.90mm 宽） 安装类型:表面贴装 包装:管件 产品目录页面:1386 (CN2011-ZH PDF) |
| LT1721CS#TR | 功能描述:IC COMP QUAD R-R 4.5NS 16SOIC RoHS:否 类别:集成电路 (IC) >> 线性 - 比较器 系列:UltraFast™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:通用 元件数:1 输出类型:CMOS，推挽式，满摆幅，TTL 电压 - 电源，单路/双路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 电压 - 输入偏移（最小值）:5mV @ 5.5V 电流 - 输入偏压（最小值）:1pA @ 5.5V 电流 - 输出（标准）:- 电流 - 静态（最大值）:24µA CMRR, PSRR（标准）:80dB CMRR，80dB PSRR 传输延迟（最大）:450ns 磁滞:±3mV 工作温度:-40°C ~ 85°C 封装/外壳:6-WFBGA，CSPBGA 安装类型:表面贴装 包装:管件 其它名称:Q3554586 |
| LT1721CS#TRPBF | 功能描述:IC COMP R-RINOUT QUAD 16-SOIC RoHS:是 类别:集成电路 (IC) >> 线性 - 比较器 系列:UltraFast™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:通用 元件数:1 输出类型:CMOS，推挽式，满摆幅，TTL 电压 - 电源，单路/双路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 电压 - 输入偏移（最小值）:5mV @ 5.5V 电流 - 输入偏压（最小值）:1pA @ 5.5V 电流 - 输出（标准）:- 电流 - 静态（最大值）:24µA CMRR, PSRR（标准）:80dB CMRR，80dB PSRR 传输延迟（最大）:450ns 磁滞:±3mV 工作温度:-40°C ~ 85°C 封装/外壳:6-WFBGA，CSPBGA 安装类型:表面贴装 包装:管件 其它名称:Q3554586 |
| LT1721IGN | 功能描述:IC COMP R-RINOUT QUAD 16-SSOP RoHS:否 类别:集成电路 (IC) >> 线性 - 比较器 系列:UltraFast™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:通用 元件数:1 输出类型:CMOS，推挽式，满摆幅，TTL 电压 - 电源，单路/双路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 电压 - 输入偏移（最小值）:5mV @ 5.5V 电流 - 输入偏压（最小值）:1pA @ 5.5V 电流 - 输出（标准）:- 电流 - 静态（最大值）:24µA CMRR, PSRR（标准）:80dB CMRR，80dB PSRR 传输延迟（最大）:450ns 磁滞:±3mV 工作温度:-40°C ~ 85°C 封装/外壳:6-WFBGA，CSPBGA 安装类型:表面贴装 包装:管件 其它名称:Q3554586 |
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