参数资料
型号: LT1721IGN#PBF
厂商: Linear Technology
文件页数: 16/28页
文件大小: 0K
描述: IC COMP R-RINOUT QUAD 16-SSOP
标准包装: 100
系列: UltraFast™
类型: 通用
元件数: 4
输出类型: CMOS,满摆幅,TTL
电压 - 电源,单路/双路(±): 2.7 V ~ 6 V
电压 - 输入偏移(最小值): 3mV @ 5V
电流 - 输入偏压(最小值): 6µA @ 5V
电流 - 输出(标准): 20mA
电流 - 静态(最大值): 7mA
CMRR, PSRR(标准): 70dB CMRR,80dB PSRR
传输延迟(最大): 10ns
磁滞: 7mV
工作温度: -40°C ~ 85°C
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
安装类型: 表面贴装
包装: 管件
LT1720/LT1721
23
17201fc
APPLICATIONS INFORMATION
Coincidence Detector
High speed comparators are especially suited for interfac-
ing pulse-output transducers, such as particle detectors,
to logic circuitry. The matched delays of a monolithic dual
are well suited for those cases where the coincidence of
two pulses needs to be detected. The circuit of Figure 19
is a coincidence detector that uses an LT1720 and discrete
components as a fast AND gate.
The reference level is set to 1V, an arbitrary threshold. Only
when both input signals exceed this will a coincidence
be detected. The Schottky diodes from the comparator
outputs to the base of the MRF-501 form the AND gate,
while the other two Schottkys provide for fast turn-off.
A logic AND gate could instead be used, but would add
considerably more delay than the 300ps contributed by
this discrete stage.
This circuit can detect coincident pulses as narrow as 3ns.
For narrower pulses, the output will degrade gracefully,
responding, but with narrow pulses that don’t rise all the
way to “high” before starting to fall. The decision delay is
4.5ns with input signals 50mV or more above the refer-
ence level. This circuit creates a TTL compatible output
but it can typically drive CMOS as well.
For a more detailed description of the operation of this
circuit, see Application Note 75, pages 10 and 11.
Figure 19. A 3ns Coincidence Detector
5V
3.9k
1k
0.1μF
51Ω
300Ω
5V
4 1N5711
MRF501
OUTPUT
GROUND
CASE LEAD
COINCIDENCE COMPARATORS
300ps AND GATE
17201 F19
1/2 LT1720
+
+
1/2 LT1720
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