参数资料
型号: LT1725IS#PBF
厂商: Linear Technology
文件页数: 19/28页
文件大小: 0K
描述: IC REG CTRLR FLYBK ISO CM 16SOIC
标准包装: 50
PWM 型: 电流模式
输出数: 1
频率 - 最大: 125kHz
占空比: 90%
电源电压: 最高 22V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
包装: 管件
产品目录页面: 1328 (CN2011-ZH PDF)
相关产品: 732-2262-6-ND - TRANS FLYBACK LT1725 20.4UH
732-2262-1-ND - TRANS FLYBACK LT1725 20.4UH
732-2262-2-ND - TRANS FLYBACK LT1725 20.4UH
LT1725
APPLICATIO S I FOR ATIO
Output Impedance Error
An additional error source is caused by transformer sec-
ondary current flow through the real life nonzero imped-
ances of the output rectifier, transformer secondary and
output capacitor. Because the secondary current only
flows during the off portion of the duty cycle, the effective
output impedance equals the “DC” lumped secondary
impedance times the inverse of the off duty cycle. If the
output load current remains relatively constant, or, in less
critical applications, the error may be judged acceptable
and the feedback resistor divider ratio adjusted for nomi-
nal expected error. In more demanding applications, out-
put impedance error may be minimized by the use of the
load compensation function (see Load Compensation).
f = switching frequency
L PRI = transformer primary side inductance
V IN = input voltage
V OUT = output voltage
t ON = output switch minimum on time
An additional constraint has to do with the minimum
enable time. The LT1725 derives its output voltage infor-
mation from the flyback pulse. If the internal minimum
enable time pulse extends beyond the flyback pulse, loss
of regulation will occur. The onset of this condition can be
determined by setting the width of the flyback pulse equal
to the sum of the flyback enable delay, t ED , plus the
minimum enable time, t EN . Minimum power delivered to
the load is then:
[
(
1 ? f ?
Minimum Power = ?
? V OUT EN ED
) ]
MINIMUM LOAD CONSIDERATIONS
The LT1725 generally provides better low load perfor-
mance than previous generation switcher/controllers uti-
lizing indirect output voltage sensing techniques.
Specifically, it contains circuitry to detect flyback pulse
“collapse,” thereby supporting operation well into discon-
2 ? L SEC ?
= V OUT ? I OUT
Which yields a minimum output constraint:
? t + t
2
(
? t ED + t EN
I OUT ( MIN ) = ?
)
tinuousmode.Nevertheless,therestillremainconstraints
to ultimate low load operation. These relate to the mini-
mum switch on time and the minimum enable time.
Discontinuous mode operation will be assumed in the
1 ? f ? V OUT ?
2 ? L SEC ?
2
where
? ( V IN ON )
Minimum Power = ?
1 ? f ? 2
2 ? L PRI ?
following theoretical derivations.
As outlined in the Operation section, the LT1725 utilizes a
minimum output switch on time, t ON . This value can be
combined with expected V IN and switching frequency to
yield an expression for minimum delivered power.
? t
= V OUT ? I OUT
This expression then yields a minimum output current
constraint:
f = switching frequency
L SEC = transformer secondary side inductance
V OUT = output voltage
t ED = enable delay time
t EN = minimum enable time
Note that generally, depending on the particulars of input
and output voltages and transformer inductance, one of
the above constraints will prove more restrictive. In other
words, the minimum load current in a particular applica-
tion will be either “output switch minimum on time”
constrained, or “minimum flyback pulse time” constrained.
(
I OUT ( MIN ) = ?
? V IN ON
)
1 ? f ?
2 ? L PRI ? V OUT ?
? t
2
where
(A final note—L PRI and L SEC refer to transformer induc-
tance as seen from the primary or secondary side respec-
tively. This general treatment allows these expressions to
be used when the transformer turns ratio is nonunity.)
1725fa
19
相关PDF资料
PDF描述
LT1725IS IC REG CTRLR FLYBK ISO CM 16SOIC
GBC60DRTN-S13 CONN EDGECARD 120POS .100 EXTEND
GBC60DRTH-S13 CONN EDGECARD 120POS .100 EXTEND
GSC17DRTF-S13 CONN EDGECARD 34POS .100 EXTEND
GMC17DRTF-S13 CONN EDGECARD 34POS .100 EXTEND
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