参数资料
型号: LT1761ES5-5#TRM
厂商: Linear Technology
文件页数: 14/22页
文件大小: 0K
描述: IC REG LDO 5V .1A TSOT23-5
标准包装: 1
稳压器拓扑结构: 正,固定式
输出电压: 5V
输入电压: 最高 20V
电压 - 压降(标准): 0.3V @ 100mA
稳压器数量: 1
电流 - 输出: 100mA
电流 - 限制(最小): 110mA
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SOT-23-5 细型,TSOT-23-5
供应商设备封装: TSOT-23-5
包装: 标准包装
其它名称: LT1761ES5-5#TRMDKR

LT1761 Series
PIN FUNCTIONS
IN (Pin 1): Input. Power is supplied to the device through
the IN pin. A bypass capacitor is required on this pin if
the device is more than six inches away from the main
input ?lter capacitor. In general, the output impedance
of a battery rises with frequency, so it is advisable to
include a bypass capacitor in battery-powered circuits. A
bypass capacitor in the range of 1μF to 10μF is suf?cient.
The LT1761 regulators are designed to withstand reverse
voltages on the IN pin with respect to ground and the OUT
pin. In the case of a reverse input, which can happen if
a battery is plugged in backwards, the device will act as
if there is a diode in series with its input. There will be
no reverse current ?ow into the regulator and no reverse
voltage will appear at the load. The device will protect both
itself and the load.
GND (Pin 2): Ground.
SHDN (Pin 3, Fixed/-SD Devices): Shutdown. The SHDN
pin is used to put the LT1761 regulators into a low power
shutdown state. The output will be off when the SHDN pin
is pulled low. The SHDN pin can be driven either by 5V logic
or open-collector logic with a pull-up resistor. The pull-up
resistor is required to supply the pull-up current of the
open-collector gate, normally several microamperes, and
the SHDN pin current, typically 1μA. If unused, the SHDN
pin must be connected to V IN . The device will not function
if the SHDN pin is not connected. For the LT1761-BYP, the
SHDN pin is internally connected to V IN .
BYP (Pins 3/4, Fixed/-BYP Devices): Bypass. The BYP
pin is used to bypass the reference of the LT1761 regula-
tors to achieve low noise performance from the regulator.
The BYP pin is clamped internally to ±0.6V (one V BE ) from
ground. A small capacitor from the output to this pin will
bypass the reference to lower the output voltage noise.
A maximum value of 0.01μF can be used for reducing
output voltage noise to a typical 20μV RMS over a 10Hz
to 100kHz bandwidth. If not used, this pin must be left
unconnected.
ADJ (Pin 4, Adjustable Devices Only): Adjust Pin. For the
adjustable LT1761, this is the input to the error ampli?er.
This pin is internally clamped to ±7V. It has a bias current
of 30nA which ?ows into the pin (see curve of ADJ Pin
Bias Current vs Temperature in the Typical Performance
Characteristics section). The ADJ pin voltage is 1.22V
referenced to ground and the output voltage range is
1.22V to 20V.
OUT (Pin 5): Output. The output supplies power to the load.
A minimum output capacitor of 1μF is required to prevent
oscillations. Larger output capacitors will be required for
applications with large transient loads to limit peak volt-
age transients. See the Applications Information section
for more information on output capacitance and reverse
output characteristics.
1761sff
14
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