参数资料
型号: LT1763IS8-3#PBF
厂商: Linear Technology
文件页数: 17/22页
文件大小: 0K
描述: IC REG LDO 3V .5A 8-SOIC
产品培训模块: More Information on LDOs
标准包装: 100
稳压器拓扑结构: 正,固定式
输出电压: 3V
输入电压: 最高 20V
电压 - 压降(标准): 0.3V @ 500mA
稳压器数量: 1
电流 - 输出: 500mA
电流 - 限制(最小): 520mA
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
LT1763 Series
APPLICATIONS INFORMATION
Y5V and Z5U capacitors, but can still be signi?cant enough
to drop capacitor values below appropriate levels. Capacitor
DC bias characteristics tend to improve as component
case size increases, but expected capacitance at operating
voltage should be veri?ed.
Voltage and temperature coef?cients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or
microphone works. For a ceramic capacitor, the stress
can be induced by vibrations in the system or thermal
transients. The resulting voltages produced can cause
appreciable amounts of noise, especially when a ceramic
capacitor is used for noise bypassing. A ceramic capacitor
produced Figure 6’s trace in response to light tapping from a
pencil. Similar vibration induced behavior can masquerade
as increased output voltage noise.
LT1763-5
C OUT = 10μF
C BYP = 0.01μF
I LOAD = 100mA
V OUT
500μV/DIV
Thermal Considerations
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C). The
power dissipated by the device will be made up of two
components:
1. Output current multiplied by the input/output voltage
differential: (I OUT )(V IN – V OUT ), and
2. GND pin current multiplied by the input voltage:
(I GND )(V IN ).
The GND pin current can be found by examining the GND
Pin Current curves in the Typical Performance Character-
istics section. Power dissipation will be equal to the sum
of the two components listed above.
The LT1763 series regulators have internal thermal limiting
designed to protect the device during overload conditions.
For continuous normal conditions, the maximum junction
temperature rating of 125°C must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction-to-ambient. Additional
heat sources mounted nearby must also be considered.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.
100ms/DIV
1763 F06
The following tables list thermal resistance for several
Figure 6. Noise Resulting from
Tapping on a Ceramic Capacitor
different board sizes and copper areas. All measurements
were taken in still air on 3/32" FR-4 board with one ounce
copper.
Table 1. DE Package, 12-Lead DFN
COPPER AREA
THERMAL RESISTANCE
TOPSIDE*
2500mm 2
1000mm 2
225mm 2
100mm 2
BACKSIDE
2500mm 2
2500mm 2
2500mm 2
2500mm 2
BOARD AREA
2500mm 2
2500mm 2
2500mm 2
2500mm 2
(JUNCTION-TO-AMBIENT)
40°C/W
45°C/W
50°C/W
60°C/W
* Device is mounted on topside
1763fg
17
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LT1763IS8-2.5#PBF IC REG LDO 2.5V .5A 8-SOIC
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