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参数资料
| 型号： | LT1765-5 |
| 厂商： | Linear Technology Corporation |
| 元件分类： | 其它接口 |
| 英文描述： | TERMINAL |
| 中文描述： | IGBT模块 |
| 文件页数： | 11/20页 |
| 文件大小： | 247K |
| 代理商： | LT1765-5 |
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
11
sn1765 1765fas
An internal comparator will force the part into shutdown
below the minimum V
IN
of 2.6V. This feature can be used
to prevent excessive discharge of battery-operated sys-
tems. If an adjustable UVLO threshold is required, the
shutdown pin can be used. The threshold voltage of the
shutdown pin comparator is 1.33V. A 3
μ
A internal current
source defaults the open pin condition to be operating (see
Typical Performance Graphs). Current hysteresis is added
above the SHDN threshold. This can be used to set voltage
hysteresis of the UVLO using the following:
R
V
V
A
R
V
)
+ μ
V
V
R
A
H
7
L
H
1
2
1 33
1 33
1
3
=
μ
=
(
.
.
V
H
– Turn-on threshold
V
L
– Turn-off threshold
Example: switching should not start until the input is
above 4.75V and is to stop if the input falls below 3.75V.
V
H
= 4.75V
V
L
= 3.75V
R
V
7
V
A
k
R
V
V
143
V
k
A
k
1
4 75
.
3 75
.
143
2
1 33
1 33
.
4 75
.
3
49 4
=
μ
=
=
(
)
+ μ
=
.
.
Keep the connections from the resistors to the SHDN pin
short and make sure that the interplane or surface capaci-
tance to the switching nodes are minimized. If high resis-
tor values are used, the SHDN pin should be bypassed with
a 1nF capacitor to prevent coupling problems from the
switch node.
SYNCHRONIZATION
The SYNC pin is used to synchronize the internal oscillator
to an external signal. The SYNC input must pass from a
logic level low, through the maximum synchronization
threshold with a duty cycle between 20% and 80%. The
input can be driven directly from a logic level output. The
synchronizing range is equal to initialoperating frequency
up to 2MHz. This means that minimumpractical sync
frequency is equal to the worst-case highself-oscillating
frequency (1.6MHz), not the typical operating frequency
of 1.25MHz. Caution should be used when synchronizing
above 1.8MHz because at higher sync frequencies the
amplitude of the internal slope compensation used to
prevent subharmonic switching is reduced. This type of
subharmonic switching only occurs at input voltages less
than twice output voltage. Higher inductor values will tend
to eliminate this problem. See Frequency Compensation
section for a discussion of an entirely different cause of
subharmonic switching before assuming that the cause is
insufficient slope compensation. Application Note 19 has
more details on the theory of slope compensation.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. Shortening
this path will also reduce the parasitic trace inductance of
approximately 25nH/inch. At switch off, this parasitic
inductance produces a flyback spike across the LT1765
switch. When operating at higher currents and input
voltages, with poor layout, this spike can generate
volt
ages across the LT1765 that may exceed its absolute
APPLICATIOU
W
U
U
Figure 5. High Speed Switching Path
1765 F05
5V
L1
SW
V
IN
LT1765
D1
C1
C3
V
IN
HIGH
FREQUENCY
CIRCULATING
PATH
LOAD
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