参数资料
型号: LT1766EFE-5
厂商: Linear Technology
文件页数: 23/30页
文件大小: 0K
描述: IC REG BUCK 5V 1.5A 16TSSOP
标准包装: 95
类型: 降压(降压)
输出类型: 固定
输出数: 1
输出电压: 5V
输入电压: 5.5 V ~ 60 V
PWM 型: 电流模式
频率 - 开关: 200kHz
电流 - 输出: 1.5A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
供应商设备封装: 16-TSSOP-EP
LT1766/LT1766-5
APPLICATIONS INFORMATION
the V C control voltage to the point where some sort of
LT1766
cycle-skipping or odd/even cycle behavior is exhibited.
CURRENT MODE
POWER STAGE
V SW
OUTPUT
In summary:
1. Be aware that the simultaneous requirements of high
g m = 2mho
ERROR
AMPLIFIER
g m =
FB
C FB
R1
TANTALUM CERAMIC
V IN , high I OUT and high f OSC may not be achievable in
practice due to internal dissipation. The Thermal Con-
siderations section offers a basis to estimate internal
GND
V C
R O
200k
2000μmho
1.22V
R LOAD
+
ESR
C1
ESL
C1
power. In questionable cases a prototype supply should
R2
be built and exercised to verify acceptable operation.
2. The simultaneous requirements of high V IN , low V OUT and
high f OSC can result in an unacceptably short minimum
switch on-time. Cycle skipping and/or odd/even cycle
behavior will result although correct output voltage is
R C
C C
C F
1766 F10
Figure 10. Model for Loop Response
usually maintained.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response, the following should be remembered—the
worse the board layout, the more dif?cult the circuit will
be to stabilize. This is true of almost all high frequency
80
60
40
20
0
–20
PHASE
GAIN
180
150
120
90
60
30
analog circuits, read the Layout Considerations section
?rst. Common layout errors that appear as stability prob-
lems are distant placement of input decoupling capacitor
and/or catch diode, and connecting the V C compensation
to a ground track carrying signi?cant switch current. In
–40
10 100 1k 10k 100k
FREQUENCY (Hz)
V IN = 42V R C = 2.2k
V OUT = 5V C C = 22nF
I LOAD = 500mA C F = 220pF
C OUT = 100μF, 10V, 0.1Ω
0
1M
1766 F11
addition, the theoretical analysis considers only ?rst order
non-ideal component behavior. For these reasons, it is
important that a ?nal stability check is made with produc-
tion layout and components.
The LT1766 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 10.
The LT1766 can be considered as two g m blocks, the error
ampli?er and the power stage.
Figure 11 shows the overall loop response. At the V C
pin, the frequency compensation components used are:
R C = 2.2k, C C = 0.022μF and C F = 220pF. The output
capacitor used is a 100μF, 10V tantalum capacitor with
typical ESR of 100mΩ.
The ESR of the tantalum output capacitor provides a use-
ful zero in the loop frequency response for maintaining
Figure 11. Overall Loop Response
stability. This ESR, however, contributes signi?cantly to
the ripple voltage at the output (see Output Ripple Volt-
age in the Applications Section). It is possible to reduce
capacitor size and output ripple voltage by replacing the
tantalum output capacitor with a ceramic output capaci-
tor because of its very low ESR. The zero provided by the
tantalum output capacitor must now be reinserted back
into the loop. Alternatively there may be cases where,
even with the tantalum output capacitor, an additional
zero is required in the loop to increase phase margin for
improved transient response.
A zero can be added into the loop by placing a resistor,
R C, at the V C pin in series with the compensation capaci-
tor, C C or by placing a capacitor, C FB , between the output
and the FB pin.
1766fc
23
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