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| 型号： | LT1767EMS8#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 13/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 1.5A 8MSOP |
| 标准包装： | 50 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.2 V ~ 20 V |
| 输入电压： | 3 V ~ 25 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1.25MHz |
| 电流 - 输出： | 1.5A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 包装： | 管件 |
| 供应商设备封装： | 8-MSOP |
| 产品目录页面： | 1329 (CN2011-ZH PDF) |
LT1767/LT1767-1.8/
LT1767-2.5/LT1767-3.3/LT1767-5
APPLICATIO N S I N FOR M ATIO N
Notice that the catch diode’s forward voltage contributes
LT1767
a significant loss in the overall system efficiency. A larger,
lower V F diode can improve efficiency by several percent.
P INDUCTOR = (I LOAD ) (L DCR )
CURRENT MODE
POWER STAGE
g m = 2.5mho
ERROR
AMPLIFIER
V SW
FB
R1
OUTPUT
TANTALUM CERAMIC
L DCR = Inductor DC resistance (assume 0.1 ? )
P INDUCTOR = (1) (0.1) = 0.1W
GND
V C
500k
g m =
850 μ mho
1.2V
+
ESR
C1
ESL
C1
Typical thermal resistance of the board is 35 ° C/W. At an
ambient temperature of 65 ° C,
T j = 65 + 40 (0.4) + 35 (0.39) = 95 ° C
R C
C C
C F
R2
If a true die temperature is required, a measurement of the
SYNC to GND pin resistance can be used. The SYNC pin
resistance across temperature must first be calibrated,
Figure 7. Model for Loop Response
1767 F07
with no device power, in an oven. The same measurement
80
180
can then be used in operation to indicate the die tempera-
ture.
60
V OUT = 5V
C OUT = 100 μ F, 0.1 ?
C C = 330pF
150
R C /C F = N/C
40
I LOAD = 500mA
120
FREQUENCY COMPENSATION
20
PHASE
90
Before starting on the theoretical analysis of frequency
response, the following should be remembered – the
0
60
worse the board layout, the more difficult the circuit will be
to stabilize. This is true of almost all high frequency analog
–20
GAIN
30
circuits, read the ‘LAYOUT CONSIDERATIONS’ section
first. Common layout errors that appear as stability prob-
–40
10
100
1k 10k
FREQUENCY (Hz)
100k
0
1M
lems are distant placement of input decoupling capacitor
and/or catch diode, and connecting the V C compensation
to a ground track carrying significant switch current. In
addition, the theoretical analysis considers only first order
non-ideal component behavior. For these reasons, it is
important that a final stability check is made with produc-
tion layout and components.
The LT1767 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 7,
with both tantalum and ceramic capacitor equivalent cir-
cuits. The LT1767 can be considered as two g m blocks, the
error amplifier and the power stage.
Figure 8 shows the overall loop response with a 330pF V C
capacitor and a typical 100 μ F tantalum output capacitor.
1767 F10
Figure 8. Overall Loop Response
Error amplifier:
DC gain set by g m and R L = 850 μ ? 500k = 425.
Pole set by C F and R L = (2 π ? 500k ? 330p) –1 = 965Hz.
Unity-gain set by C F and g m = (2 π ? 330p ? 850 μ –1 ) –1 =
410kHz.
Power stage:
DC gain set by g m and R L (assume 10 ? ) = 2.5 ? 10 = 25.
Pole set by C OUT and R L = (2 π ? 100 μ ? 10) –1 = 159Hz.
Unity-gain set by C OUT and g m = (2 π ? 100 μ ? 2.5 –1 ) –1 =
3.98kHz.
Tantalum output capacitor:
Zero set by C OUT and C ESR = (2 π ? 100 μ ? 0.1) –1 = 15.9kHz.
The response is set by the following terms:
sn1767 1767fas
13
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