参数资料
型号: LT1769
厂商: Linear Technology Corporation
英文描述: Constant-Current/ Constant-Voltage 2A Battery Charger with Input Current Limiting
中文描述: 恒流/恒压电池充电器,带甲输入限流
文件页数: 15/16页
文件大小: 214K
代理商: LT1769
15
LT1769
APPLICATIO
S I
FOR
ATIO
U
Lower Dropout Voltage
For even lower dropout and/or reducing heat on the board,
the input diode D3 can be replaced with a FET (see Figure
11). Connect a P-channel FET in place of the input diode
with its gate connected to the battery causing the FET to
turn off when the input voltage goes low. The problem is
that the gate must be pumped low so that the FET is fully
turned on even when the input is only a volt or two above
the battery voltage. Also there is a turn-off speed issue.
The FET should turn off instantly when the input is dead
shorted to avoid large current surges from the battery
back through the charger into the FET. Gate capacitance
slows turn-off, so a small P-channel (Q2) is added to
discharge the gate capacitance quickly in the event of an
input short. The Q2 body diode creates the necessary
pumping action to keep the gate of Q1 low during normal
operation. Note that Q1 and Q2 have a V
GS
spec limit of
20V. This restricts V
IN
to a maximum of 20V. For low
dropout operation with V
IN
> 20V consult factory.
W
U
U
Optional Diode Connections
The typical application in Figure 1 shows a single diode
(D3) to isolate the V
CC
pin from the adaptor input and to
block reverse input voltage (both steady state and tran-
sient). This simple connection may be unacceptable in
situations where the system load must be powered from
the battery when the adapter input power is removed. As
shown in Figure 12, a parasitic diode exists from the SW
pin to the V
CC
pin in the LT1769. When the input power is
removed, this diode will become forward biased and will
provide a current path from the battery to the system load.
Because of diode power limitations, it is not recom-
mended to power the system load through the internal
parasitic diode. To safely power the system load from the
battery, an additional Schottky diode (D4) is needed. For
minimum losses, D4 could be replaced by a low R
DS(ON)
MOSFET which is turned on when the adapter power is
removed.
Layout Considerations
Switch rise and fall times are under 10ns for maximum
efficiency. To minimize radiation, the catch diode, SW pin
and input bypass capacitor leads should be kept as short
as possible. A ground plane should be used under the
switching circuitry to prevent interplane coupling and to
act as a thermal spreading path. All ground pins should be
connected to expanded traces for low thermal resistance.
The fast-switching high current ground path, including the
switch, catch diode and input capacitor, should be kept
very short. Catch diode and input capacitor should be
close to the chip and terminated to the same point. This
path contains nanosecond rise and fall times with several
amps of current. The other paths contain only DC and/or
200kHz tri-wave and are less critical. Figure 13 indicates
the high speed, high current switching path. Figure 14
shows critical path layout. Contact Linear Technology for
the LT1769 circuit PCB layout or Gerber file.
SW
L1
CLP
CLN
ADAPTER
IN
TO
SYSTEM
LOAD
R
S1
C
IN
R
S4
R7
500
C1
1
μ
F
D3
LT1769
INTERNAL
PARASITIC
DIODE
V
CC
1769 F12a
D4
+
+
+
Figure 12. Modified Diode Connection
Figure 13. High Speed Switching Path
1769 F13
V
BAT
L1
V
IN
HIGH
FREQUENCY
CIRCULATING
PATH
BAT
SWITCH NODE
C
IN
C
OUT
D1
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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