参数资料
型号: LT1776IS8#TR
厂商: Linear Technology
文件页数: 13/20页
文件大小: 0K
描述: IC REG BUCK ADJ 0.7A 8SOIC
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.24 V ~ 34 V
输入电压: 7.4 V ~ 40 V
PWM 型: 电流模式,混合
频率 - 开关: 200kHz
电流 - 输出: 700mA
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
供应商设备封装: 8-SOIC
LT1776
APPLICATIO N S I N FOR M ATIO N
The high speed switching current path is shown schemati-
cally in Figure 3. Minimum lead length in these paths is
essential to ensure clean switching and minimal EMI. The
paths containing the input capacitor, output switch and
output diode are the only ones containing nanosecond rise
and fall times. Keep these paths as short as possible.
V IN
As an example, assume that the capacitance between the
V SW node and a high impedance pin node is 0.1pF, and
further assume that the high impedance node in question
exhibits a capacitance of 1pF to ground. Due to the high
dV/dt, large excursion behavior of the V SW node, this will
couple a nearly 4V transient to the high impedance pin,
causing abnormal operation. (This assumes the “typical”
40V IN to 5V OUT application.) An explicit 100pF capacitor
added to the node will reduce the amplitude of the distur-
bance to more like 50mV (although settling time will
V IN
+
C1
LT1776
V SW
+
V OUT
increase).
Specific pin recommendations are as follows:
D1
C2
1776 F03
Figure 3. High Speed Current Switching Paths
Additionally, it is possible for the LT1776 to cause EMI
problems by “coupling to itself”. Specifically, this can
occur if the V SW pin is allowed to capacitively couple in an
uncontrolled manner to the part’s high impedance nodes,
i.e., SHDN, SYNC, V C and FB. This can cause erratic
operation such as odd/even cycle behavior, pulse width
SHDN: If unused, add a 100pF capacitor to ground.
SYNC: Ground if unused.
V C : Add a capacitor directly to ground in addition to the
explicit compensation network. A value of one-tenth of
the main compensation capacitor is recommended, up
to a maximum of 100pF.
FB: Assuming the V C pin is handled properly, this pin
usually requires no explicit capacitor of its own, but
keep this node physically small to minimize stray
capacitance.
“nervousness”, improper output voltage and/or prema-
ture current limit action.
13
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