参数资料
型号: LT1933HDCB#TRPBF
厂商: Linear Technology
文件页数: 16/20页
文件大小: 0K
描述: IC REG BUCK ADJ 0.6A 6DFN
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.25 V ~ 31.7 V
输入电压: 3.6 V ~ 36 V
PWM 型: 电流模式
频率 - 开关: 500kHz
电流 - 输出: 600mA
同步整流器:
工作温度: -40°C ~ 150°C
安装类型: 表面贴装
封装/外壳: 6-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 6-DFN-EP(2x3)
LT1933
APPLICATIONS INFORMATION
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Figure 8 shows
the recommended component placement with trace,
ground plane and via locations. Note that large, switched
currents ?ow in the LT1933’s V IN and SW pins, the catch
diode (D1) and the input capacitor (C2). The loop formed
by these components should be as small as possible and
tied to system ground in only one place. These components,
along with the inductor and output capacitor, should be
placed on the same side of the circuit board, and their
connections should be made on that layer. Place a local,
V OUT
unbroken ground plane below these components, and tie
this ground plane to system ground at one location, ideally
at the ground terminal of the output capacitor C1. The SW
and BOOST nodes should be as small as possible. Finally,
keep the FB node small so that the ground pin and ground
traces will shield it from the SW and BOOST nodes. Include
two vias near the GND pin of the LT1933 to help remove
heat from the LT1933 to the ground plane.
Figure 8a shows the layout for the DFN package. Vias
near and under the exposed die attach paddle minimize
the thermal resistance of the LT1933.
V IN
GND
VIAS
C1
D1
(8a)
C2
1933 F08a
DFN Package
SHUTDOWN
V IN
C1
V OUT
VIAS
C2
D1
1933 F08b
SYSTEM
GROUND
OUTLINE OF LOCAL GROUND PLANE
(8b)
SOT-23 Package
Figure 8. A Good PCB Layout Ensures Proper, Low EMI Operation
1933fe
16
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