参数资料
型号: LT1945IMS#TRPBF
厂商: Linear Technology
文件页数: 4/8页
文件大小: 0K
描述: IC REG MULTI CONFIG ADJ 10MSOP
标准包装: 2,500
类型: 升压(升压),反相,回扫,Sepic
输出类型: 可调式
输出数: 2
输出电压: 1.23 V ~ 36 V
输入电压: 1.2 V ~ 15 V
电流 - 输出: 350mA
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
包装: 带卷 (TR)
供应商设备封装: 10-MSOP
LT1945
PIN FUNCTIONS
NFB1 (Pin 1): Feedback Pin for Switcher 1. Set the output
voltage by selecting values for R1 and R2.
SHDN1 (Pin 2): Shutdown Pin for Switcher 1. Tie this
pin to 0.9V or higher to enable device. Tie below 0.25V
to turn it off.
GND (Pin 3): Ground. Tie this pin directly to the local
ground plane.
SHDN2 (Pin 4): Shutdown Pin for Switcher 2. Tie this
pin to 0.9V or higher to enable device. Tie below 0.25V
to turn it off.
FB2 (Pin 5): Feedback Pin for Switcher 2. Set the output
voltage by selecting values for R1B and R2B.
BLOCK DIAGRAM
SW2 (Pin 6): Switch Pin for Switcher 2. This is the
collector of the internal NPN power switch. Minimize the
metal trace area connected to the pin to minimize EMI.
PGND (Pins 7, 9): Power Ground. Tie these pins directly
to the local ground plane. Both pins must be tied.
V IN (Pin 8): Input Supply Pin. Bypass this pin with a
capacitor as close to the device as possible.
SW1 (Pin 10): Switch Pin for Switcher 1. This is the
collector of the internal NPN power switch. Minimize the
metal trace area connected to the pin to minimize EMI.
V IN
C1
L1
C3
D1
L2
V OUT1
C2
V OUT2
C4
D2
L3
V IN
8
V IN
2
SHDN1
10
SW1
SW2
6
SHDN2
4
V IN
R5
80k
R6
80k
R6B
40k
R5B
40k
+
A1
ENABLE
ENABLE
A1B
+
V OUT2
Q1
Q2
X10
R3
60k
400ns
ONE-SHOT
RESET
DRIVER
Q3
Q3B
DRIVER
400ns
ONE-SHOT
RESET
Q2B
X10
R3B
30k
Q1B
5
FB2
R1B
(EXTERNAL)
R2B
(EXTERNAL)
+
+
V OUT1
R4
280k
0.12Ω
0.12Ω
R4B
140k
R1
(EXTERNAL)
NFB1
1
SWITCHER 1
A2
42mV
42mV
A2B
SWITCHER 2
R2
(EXTERNAL)
3
GND
9
PGND
PGND
7
1945 BD
Figure 1. LT1945 Block Diagram
OPERATION
The LT1945 uses a constant off-time control scheme
to provide high ef?ciencies over a wide range of output
current. Operation can be best understood by referring
to the block diagram in Figure 1. Q1 and Q2 along with
R3 and R4 form a bandgap reference used to regulate
the output voltage. When the voltage at the NFB1 pin is
slightly below –1.23V, comparator A1 disables most of
the internal circuitry. Output current is then provided by
capacitor C2, which slowly discharges until the voltage
at the NFB1 pin goes above the hysteresis point of A1
(typical hysteresis at the NFB1 pin is 8mV). A1 then enables
the internal circuitry, turns on power switch Q3, and the
1945fa
4
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