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参数资料
| 型号： | LT1950EGN#TR |
| 厂商： | Linear Technology |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR PWM CM 16-SSOP |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 560kHz |
| 占空比： | 97% |
| 电源电压： | 3 V ~ 25 V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
LT1950
OPERATIO
increases the range of MOSFETs that can be selected and
allows applications requiring high gate drive with a large
swing in V IN voltage. When V IN2 exceeds 8V, the GATE
output driver is enabled. The GATE switches between 0V
and V IN2 at a constant frequency set by a resistor from the
R OSC pin to ground. When V IN2 reaches 11V, the internal
switcher at the BOOST pin is disabled to save power and
only re-enabled when V IN2 drops below 10V. The internal
boost switcher runs in burst mode operation, asynchro-
nous to the main oscillator. If low V IN operation with high
GATE drive is not required, the BOOST pin is left open and
the V IN2 pin shorted to V IN . With V IN2 shorted to V IN the
minimum operational V IN voltage will increase from 3V to
8V (required at V IN2 to enable the GATE output driver). For
GATE turn on, a PWM latch is set at the start of each main
oscillator cycle. For GATE turn off, the PWM latch is reset
when either the current sense comparator is tripped, the
maximum duty cycle is reached, or the BLANK override
threshold is exceeded.
A resistor divider from the application’s output voltage
generates a voltage at the FB pin that is compared to the
internal 1.23V reference by the error amplifier. The error
amplifier output (COMP) defines the input threshold
(I SENSE ) of the current sense comparator. Maximum I SENSE
voltage is clamped to 100mV. By connecting I SENSE to a
sense resistor in series with the source of the external
MOSFET, the peak switch current is controlled by COMP.
An increase in output load current causing the output
voltage to fall, will cause COMP to rise, increasing I SENSE
threshold, increasing the current delivered to the output.
This current mode technique means that the error ampli-
fier commands current to be delivered to the output rather
than voltage. This makes frequency compensation easier
and provides faster loop response to output load tran-
sients.
The current mode architecture requires slope compensa-
tion to be added to the current sensing loop to prevent
subharmonic oscillations which can occur for duty cycles
above 50%. Unlike most current mode converters which
have a slope compensation ramp that is fixed internally,
compensation. A default level of slope compensation is
achieved with the SLOPE pin open. Increased slope com-
pensation can be programmed by reducing the value of
resistance inserted between the SLOPE pin and V REF pin.
A SYNC pin allows the LT1950 main oscillator to be
synchronized to an external clock . To avoid loss of slope
compensation during synchronization, the free running
main oscillator frequency should be programmed to ap-
proximately 80% of the external clock frequency.
The LT1950 can be placed into shutdown mode when the
SHDN pin drops below an accurate 1.32V threshold. This
threshold can be used to program undervoltage lockout
(UVLO) at V IN for current limited or high source resistance
supplies. SHDN pin current hysteresis also exists to allow
external programming of UVLO voltage hysteresis. When
V IN and V IN2 exceed internally set UVLO thresholds of 2.6V
and 6.8V, the V REF output becomes active. The V REF output
is a 2.5V reference supplying the majority of LT1950
control circuitry and capable of sourcing up to 2.5mA for
external use.
To prevent noise in the system causing premature turn off
of the external MOSFET the LT1950 has leading edge
blanking. This means the current sense comparator out-
put is ignored during MOSFET turn on and for an extended
period after turn on. The extended blanking period is
adjusted by inserting a resistor from the BLANK pin to
ground. A short to ground defines a minimum default
blanking period. Increased resistance from the BLANK pin
to ground will increase blanking duration. Fault conditions
causing I SENSE to exceed 125mV will override blanking
and reduce the I SENSE to GATE delay to 60ns.
For applications requiring maximum duty cycle clamping,
the V SEC pin reduces duty cycle for increased voltage on
the pin. The V SEC pin provides a volt-second clamp critical
in forward converter applications.
Maximum duty cycle follows (105/V SEC )% for V SEC volt-
ages between 1.4V to 2.8V. If unused, the V SEC pin should
be shorted to ground, leaving the natural maximum duty
cycle of the part to be typically 95% for 200kHz operation.
placing a constraint on inductor value and operating
frequency, the LT1950 has externally adjustable slope
1950fa
9
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LT1950IGN | 功能描述:IC REG CTRLR PWM CM 16-SSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
| LT1950IGN#PBF | 功能描述:IC REG CTRLR PWM CM 16-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,000 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:1MHz 占空比:50% 电源电压:9 V ~ 10 V 降压:无 升压:是 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:8-TSSOP（0.173"，4.40mm 宽） 包装:带卷 (TR) |
| LT1950IGN#TR | 功能描述:IC REG CTRLR PWM CM 16-SSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
| LT1950IGN#TRPBF | 功能描述:IC REG CTRLR PWM CM 16-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
| LT1952 | 制造商:LINER 制造商全称:Linear Technology 功能描述:2-Phase Step-Up DC/DC Controller |
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