参数资料
型号: LT1959CR#TR
厂商: Linear Technology
文件页数: 18/24页
文件大小: 0K
描述: IC REG BUCK ADJ 4.5A D2PAK
标准包装: 750
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.21 V ~ 38 V
输入电压: 4.3 V ~ 15 V
PWM 型: 电流模式
频率 - 开关: 500kHz
电流 - 输出: 4.5A
同步整流器:
工作温度: 0°C ~ 125°C
安装类型: 表面贴装
封装/外壳: TO-263-8,D²Pak(7 引线+接片),TO-263CA
包装: 带卷 (TR)
供应商设备封装: D2PAK-7
LT1959
APPLICATIO N S I N FOR M ATIO N
formulas show how to calculate each of these losses.
These formulas assume continuous mode operation, so
they should not be used for calculating efficiency at light
load currents.
Switch loss:
T J = T A + θ JA (P TOT )
With the SO-8 package ( θ JA = 80 ° C/W), at an ambient
temperature of 50 ° C,
T J = 50 + 80 (0.87) = 120 ° C
( ) ( V OUT ) + 24 ns ( I )( V )( f )
V IN
P SW =
R SW I OUT
2
OUT IN
Die temperature is highest at low input voltage, so use
lowest continuous input operating voltage for thermal
calculations.
Boost current loss:
FREQUENCY COMPENSATION
(
P BOOST =
2
V OUT I OUT / 50
V IN
Quiescent current loss:
)
Loop frequency compensation of switching regulators
can be a rather complicated problem because the reactive
components used to achieve high efficiency also
introduce multiple poles into the feedback loop. The
inductor and output capacitor on a conventional step-
( )
? V OUT ? 0 . 002
P Q = V IN ( 0 . 001 ) + V OUT
( 0 . 005 ) +
? 2 ?
? ?
V IN
down converter actually form a resonant tank circuit that
can exhibit peaking and a rapid 180 ° phase shift at the
resonant frequency. By contrast, the LT1959 uses a “cur-
rent mode” architecture to help alleviate phase shift cre-
( 0 . 07 )( 3 ) ( 5 ) + ? 24 ? 10 ? ( 3 )( 10 ) ? 500 ? 10 ?
=
P SW
? ? ? ?
( ) ( ) = 0 . 15 W
( 5 ) ( 0 . 002 ) = 0 . 04 W
= 10 ( ) + 5 ( ) +
V SW
g m = 5.3A/V
R1
R SW = Switch resistance (≈0.07)
24ns = Equivalent switch current/voltage overlap time
f = Switch frequency
Example: with V IN = 10V, V OUT = 5V and I OUT = 3A:
2
? 9 3
10
= 0 . 32 + 0 . 36 = 0 . 68 W
2
5 3 / 50
P BOOST =
10
2
P Q 0 . 001 0 . 005
10
ated by the inductor. The basic connections are shown in
Figure 9. Figure 10 shows a Bode plot of the phase and gain
of the power section of the LT1959, measured from the V C
pin to the output. Gain is set by the 5.3A/V transconduc-
tance of the LT1959 power section and the effective
complex impedance from output to ground. Gain rolls off
smoothly above the 600Hz pole frequency set by the
100 μ F output capacitor. Phase drop is limited to about
70 ° . Phase recovers and gain levels off at the zero fre-
quency ( ≈ 16kHz) set by capacitor ESR (0.1 ? ).
LT1959
CURRENT MODE
POWER STAGE OUTPUT
ERROR
AMPLIFIER
FB
Total power dissipation is 0.68 + 0.15 + 0.04 = 0.87W.
Thermal resistance for LT1959 package is influenced by
the presence of internal or backside planes. With a full
plane under the SO package, thermal resistance will be
about 80 ° C/W. No plane will increase resistance to about
120 ° C/W. To calculate die temperature, use the proper
GND
C F
V C
R C
C C
1.21V
R2
+
ESR
C1
thermal resistance number for the desired package and
add in worst-case ambient temperature:
18
Figure 9. Model for Loop Response
1959 F09
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