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| 型号： | LT1959CS8 |
| 厂商： | Linear Technology |
| 文件页数： | 20/24页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 4.5A 8SOIC |
| 标准包装： | 100 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.21 V ~ 38 V |
| 输入电压： | 4.3 V ~ 15 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 500kHz |
| 电流 - 输出： | 4.5A |
| 同步整流器： | 无 |
| 工作温度： | 0°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 管件 |
| 供应商设备封装： | 8-SOIC |
LT1959
APPLICATIO N S I N FOR M ATIO N
G MP = Transconductance of power stage = 5.3A/V
G MA = Error amplifier transconductance = 2(10 –3 )
ESR = Output capacitor ESR
1.21 = Reference voltage
With V OUT = 5V and ESR = 0.03 ? , a value of 6.5k for R C
would yield zero gain margin, so this represents an upper
limit. There is a second limitation however which has
nothing to do with theoretical small signal dynamics. This
resistor sets high frequency gain of the error amplifier,
cases, the resistor may have to be larger to get acceptable
phase response, and some means must be used to control
ripple voltage at the V C pin. The suggested way to do this
is to add a capacitor (C F ) in parallel with the R C /C C network
on the V C pin. Pole frequency for this capacitor is typically
set at one-fifth of switching frequency so that it provides
significant attenuation of switching ripple, but does not
add unacceptable phase shift at loop unity-gain frequency.
With R C = 6k,
(
) ( )
2 π 500 × 10 6 k
includingthegainattheswitchingfrequency.Ifswitching
frequency gain is high enough, output ripple voltage will
appear at the V C pin with enough amplitude to muck up
proper operation of the regulator. In the marginal case,
C F =
5
( 2 π )( f )( R C )
=
5
3
= 275 pF
( R C )( G MA ) ( V IN ? V OUT )( ESR )( 1 . 21 )
( V IN )( )( ) f
V C ( ) =
( = 6 k ) ( ) 3 ? ( )( )( ) = 0 . 144 V
( 10 ) ( 10 ? 10 ? 6 )( 500 ? 10 3 )
V C ( )
subharmonic switchingoccurs,asevidencedbyalternat-
ing pulse widths seen at the switch node. In more severe
cases, the regulator squeals or hisses audibly even though
the output voltage is still roughly correct. None of this will
show on a theoretical Bode plot because Bode is an
amplitude insensitive analysis. Tests have shown that if
ripple voltage on the V C is held to less than 100mV P-P , the
LT1959 will be well behaved. The formula below will give
an estimate of V C ripple voltage when R C is added to the
loop, assuming that R C is large compared to the reactance
of C C at 500kHz.
RIPPLE
L
G MA = Error amplifier transconductance (2000 μ Mho)
If a computer simulation of the LT1959 showed that a
series compensation resistor of 6k gave best overall loop
response, with adequate gain margin, the resulting V C pin
ripple voltage with V IN = 10V, V OUT = 5V, ESR = 0.1 ? ,
L = 10 μ H, would be:
2 ? 10 10 ? 5 0 . 1 1 . 21
RIPPLE
This ripple voltage is high enough to possibly create
subharmonic switching. In most situations a compromise
value (< 2k in this case) for the resistor gives acceptable
phase margin and no subharmonic problems. In other
20
How Do I Test Loop Stability?
The “standard” compensation for LT1959 is a 1.5nF
capacitor for C C , with R C = 0. While this compensation will
work for most applications, the “optimum” value for loop
compensation components depends, to various extent, on
parameters which are not well controlled. These include
inductor value ( ± 30% due to production tolerance, load
current and ripple current variations), output capacitance
( ± 20% to ± 50% due to production tolerance, tempera-
ture, aging and changes at the load), output capacitor ESR
( ± 200% due to production tolerance, temperature and
aging), and finally, DC input voltage and output load
current . This makes it important for the designer to check
out the final design to ensure that it is “robust” and tolerant
of all these variations.
I check switching regulator loop stability by pulse loading
the regulator output while observing transient response at
the output, using the circuit shown in Figure 13. The
regulator loop is “hit” with a small transient AC load
current at a relatively low frequency, 50Hz to 1kHz. This
causes the output to jump a few millivolts, then settle back
to the original value, as shown in Figure 14. A well behaved
loop will settle back cleanly, whereas a loop with poor
phase or gain margin will “ring” as it settles. The number
of rings indicates the degree of stability, and the frequency
of the ringing shows the approximate unity-gain fre-
quency of the loop. Amplitude of the signal is not particu-
larly important, as long as the amplitude is not so high that
the loop behaves nonlinearly.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LT1959CS8#PBF | 功能描述:IC REG BUCK ADJ 4.5A 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:250 系列:- 类型:降压（降压） 输出类型:固定 输出数:1 输出电压:1.2V 输入电压:2.05 V ~ 6 V PWM 型:电压模式 频率 - 开关:2MHz 电流 - 输出:500mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:6-UFDFN 包装:带卷 (TR) 供应商设备封装:6-SON（1.45x1） 产品目录页面:1032 (CN2011-ZH PDF) 其它名称:296-25628-2 |
| LT1959CS8#TR | 功能描述:IC REG BUCK ADJ 4.5A 8SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 设计资源:Design Support Tool 标准包装:1 系列:- 类型:升压（升压） 输出类型:固定 输出数:1 输出电压:3V 输入电压:0.75 V ~ 2 V PWM 型:- 频率 - 开关:- 电流 - 输出:100mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:SOT-23-5 细型，TSOT-23-5 包装:剪切带 (CT) 供应商设备封装:TSOT-23-5 其它名称:AS1323-BTTT-30CT |
| LT1959CS8#TRPBF | 功能描述:IC REG BUCK ADJ 4.5A 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 设计资源:Design Support Tool 标准包装:1 系列:- 类型:升压（升压） 输出类型:固定 输出数:1 输出电压:3V 输入电压:0.75 V ~ 2 V PWM 型:- 频率 - 开关:- 电流 - 输出:100mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:SOT-23-5 细型，TSOT-23-5 包装:剪切带 (CT) 供应商设备封装:TSOT-23-5 其它名称:AS1323-BTTT-30CT |
| LT1959I | 制造商:LINER 制造商全称:Linear Technology 功能描述:4.5A, 500kHz Step-Down Switching Regulator |
| LT1959IR | 功能描述:IC REG BUCK ADJ 4.5A D2PAK RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 设计资源:Design Support Tool 标准包装:1 系列:- 类型:升压（升压） 输出类型:固定 输出数:1 输出电压:3V 输入电压:0.75 V ~ 2 V PWM 型:- 频率 - 开关:- 电流 - 输出:100mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:SOT-23-5 细型，TSOT-23-5 包装:剪切带 (CT) 供应商设备封装:TSOT-23-5 其它名称:AS1323-BTTT-30CT |
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