参数资料
型号: LT1961EMS8E#TRPBF
厂商: Linear Technology
文件页数: 12/16页
文件大小: 0K
描述: IC REG BOOST ADJ 1.5A 8MSOP
标准包装: 2,500
类型: 升压(升压)
输出类型: 可调式
输出数: 1
输出电压: 1.2 V ~ 35 V
输入电压: 3 V ~ 25 V
PWM 型: 电流模式
频率 - 开关: 1.25MHz
电流 - 输出: 1.5A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 8-MSOP-EP
LT1961
APPLICATIO N S I N FOR M ATIO N
DC , duty cycle =
=
( V OUT )( I OUT )
= ( DC )( I ) + 17 n ( I )( V )( )
P SW SW SW SW OUT f
) ( R
THERMAL CALCULATIONS
Power dissipation in the LT1961 chip comes from four
sources: switch DC loss, switch AC loss, drive current, and
input quiescent current. The following formulas show how
to calculate each of these losses. These formulas assume
continuous mode operation, so they should not be used
for calculating efficiency at light load currents.
(V OUT ? V IN )
V OUT
I SW
V IN
Switch loss:
2
V IN loss:
with no device power, in an oven. The same measurement
can then be used in operation to indicate the die tempera-
ture.
FREQUENCY COMPENSATION
Loop frequency compensation is performed on the output
of the error amplifier (V C pin) with a series RC network.
The main pole is formed by the series capacitor and the
output impedance ( ≈ 500k Ω ) of the error amplifier. The
pole falls in the range of 2Hz to 20Hz. The series resistor
creates a “zero” at 1kHz to 5kHz, which improves loop
stability and transient response. A second capacitor, typi-
cally one-tenth the size of the main compensation capaci-
tor, is sometimes used to reduce the switching frequency
ripple on the V C pin. V C pin ripple is caused by output
voltage ripple attenuated by the output divider and multi-
plied by the error amplifier. Without the second capacitor,
V C pin ripple is:
P VIN =
+ 1 mA ( V IN )
(V IN )(I SW )(DC )
50
R SW = Switch resistance ( ≈ 0.27 Ω hot)
V C Pin Ripple =
1.2(V RIPPLE )(g m )(R C )
(V OUT )
Example: V IN = 5V, V OUT = 12V and I OUT = 0.5A
Total power dissipation = 0.23 + 0.31 + 0.07 + 0.005 =
0.62W
Thermal resistance for LT1961 package is influenced by
the presence of internal or backside planes. With a full
plane under the package, thermal resistance will be about
50 ° C/W. To calculate die temperature, use the appropriate
thermal resistance number and add in worst-case ambient
temperature:
T J = T A + θ JA (P TOT )
If a true die temperature is required, a measurement of the
SYNC to GND pin resistance can be used. The SYNC pin
V RIPPLE = Output ripple (V P–P )
g m = Error amplifier transconductance
( ≈ 850 μ mho)
R C = Series resistor on V C pin
V OUT = DC output voltage
To prevent irregular switching, V C pin ripple should be
kept below 50mV P–P . Worst-case V C pin ripple occurs at
maximum output load current and will also be increased if
poor quality (high ESR) output capacitors are used. The
addition of a 47pF capacitor on the V C pin reduces switch-
ing frequency ripple to only a few millivolts. A low value for
R C will also reduce V C pin ripple, but loop phase margin
may be inadequate.
resistance across temperature must first be calibrated,
1961fa
12
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